Document
TS5070 TS5071
PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
COMPLETE CODEC AND FILTER SYSTEM INCLUDING : – TRANSMIT AND RECEIVE PCM CHANNEL FILTERS – µ -LAW OR A-LAW COMPANDING CODER AND DECODER – RECEIVE POWER AMPLIFIER DRIVES 300 Ω – 4.096 MHz SERIAL PCM DATA (max) PROGRAMMABLE FUNCTIONS : – TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB STEPS – RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB STEPS – HYBRID BALANCE CANCELLATION FILTER – TIME-SLOT ASSIGNMENT: UP TO 64 SLOTS/FRAME – 2 PORT ASSIGNMENT (TS5070) – 6 INTERFACE LATCHES (TS5070) – A OR µ-LAW – ANALOG LOOPBACK – DIGITAL LOOPBACK DIRECT INTERFACE TO SOLID-STATE SLICs SIMPLIFIES TRANSFORMER SLIC, SINGLE WINDING SECONDARY STANDARD SERIAL CONTROL INTERFACE 80 mW OPERATING POWER (typ) 1.5mW STANDBY POWER (typ) MEETS OR EXCEEDS ALL CCITT AND LSSGR SPECIFICATIONS TTL AND CMOS COMPATIBLE DIGITAL INTERFACES DESCRIPTION The TS5070series are the second generationcombined PCM CODEC and Filter devices optimized for digital switching applications on subscriber and trunk line cards. Using advanced switched capacitor techniques the TS5070 and TS5071 combine transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional serial PCM interface capable of being clocked up to 4.096 MHz. A number of programmable functions may be controlled via a serial control port.
December 1997
DIP20 (Plastic) ORDERING NUMBER: TS5071N
PLCC28 ORDERING NUMBERS: TS5070FN TS5070FNTR
Channel gains are programmable over a 25.4 dB range in each direction, and a programmable filter is included to enable Hybrid Balancing to be adjusted to suit a wide range of loop impedance conditions. Both transformer and active SLIC interface circuits with real or complex termination impedances can be balanced by this filter, with cancellation in excess of 30 dB being readily achievable when measured across the passbandagainst standardtest termination networks. To enable COMBO IIG to interface to the SLIC control leads, a number of programmable latches are included ; each may be configured as either an input or an output. The TS5070 provides 6 latches and the TS5071 5 latches.
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TS5070 PIN FUNCTIONALITY (PLCC28)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name GND VFR0 VSS NC NC IL3 IL2 FSR D R1 D R0 CO CI CCLK CS MR BCLK MCLK DX0 DX1 TSX0 TSX1 FSX IL5 IL4 IL1 IL0 VCC VFXI Function Ground Input (+0V) Analog Output Supply Input (-5V) Not Connected Not Connected Digital Input or Output defined by LDR register content Digital Input or Output defined by LDR register content Digital input Digital input sampled by BCLK falling edge Digital input sampled by BCLK falling edge Digital output (shifted out on CCLK rising edge) Digital input (sampled on CCLK falling edge) Digital input (clock) Digital input (chip select for CI/CO) Digital Input Digital input (clock) Digital input Digital output clocked by BCLK rising edge Digital output clocked by BCLK rising edge Open drain output (pulled low by active DX0 time slot) Open drain output (pulled low by active DX1 time slot) Digital input Digital input or output defined by LDR register content Digital input or output defined by LDR register content Digital input or output defined by LDR register content Digital input or output defined by LDR register content Supply input (+5V) Analog input
TS5070 FUNCTIONAL DIAGRAM
VCC=+5V VFXI ENCODER
AZ
VSS=-5V
TX GAIN
TX TIME SLOT
TX REGISTER
DX0 DX1 TSX0
HYBRID BALANCE FILTER
HYBAL 1 HYBAL 2 HYBAL 3
Vref TIME-SLOT ASSIGNMENT
CTL REG.
TSX1 FSX BCLK FSR
VFRO
RX REGISTER
DR0 DR1 MCLK
GND
TS5070/71
RX TIME SLOT
DECODER IL5 IL4 IL3 IL2 IL1 IL0
D94TL135
MR
RX GAIN
CS CONTROL INTERFACE CCLK CO CI
INTERFACE LATCHES
LATCH DIR LATCH CONT.
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BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VSS VIN IO Tstg Tlead VCC to GND VSS to GND Voltage at VFXI Voltage at Any Digital Input Current at VFRO Current at Any Digital Output Storage Temperature Range Lead Temperature Range (soldering, 10 seconds) Parameter Value 7 –7 VCC + 0.5 to VSS – 0.5 VCC + 0.5 to GND – 0.5 ± 100 ± 50 – 65, + 150 300 Unit V V V V mA mA °C °C
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PIN CONNECTIONS
PLCC28 TS5070FN
DIP20 TS5071N
POWER SUPPLY, CLOCK
Name VCC VSS GND BCLK Pin Type S S S I TS5070 FN 27 3 1 16 TS5071 N 19 3 1 12 Function Positive Power Supply Negative Power Supply Ground Bit Clock +5V±5% – 5 V± 5% All analog and digital signals are referenced to this pin. Bit clock input used to shift PCM data into and out of the DR and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK (TS5071 only). Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1. 536/1. 544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. Description
MCLK
I
17
12
.