TZA3015HW

INTEGRATED CIRCUITS DATA SHEET TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate™ 4-bit fibre optic transceiver Preliminary specification Supersedes data of 2003 Oct 06 2003 Dec 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate™ 4-bit fibre optic transceiver FEATURES General A-rabitte™(1): supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one single reference frequency 4-bit parallel interface Selectable Double Data Rate (DDR, half clock rate) or Single Data Rate (SDR) clocking scheme on parallel interface, enabling easy interfacing with FPGA devices I2C-bus and pin programmable Six selectable reference frequency ranges Transmitter, receiver and transceiver modes Clean-up loop back mode Line loop back mode Diagnostic loop back mode Serial loop timing mode Single 3.3 V power supply. Limiter Limiting amplifier with typical 5 mV input sensitivity Received Signal Strength Indicator (RSSI) Loss Of Signal (LOS) indicator with adjustable threshold Differential overvoltage protection. Data and clock recovery and synthesizer Supports any bit rate from 30 Mbit/s to 3.2 Gbit/s when using I2C-bus interface Supports eight pre-programmed (pin selectable) bit rates: – SDH/SONET rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and 2666.06 Mbit/s (STM16/OC48 + FEC) – Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s – Fibre Channel at 1062.5 Mbit/s and 2125 Mbit/s. Provides stable clock signal at LOS Frequency lock indic...