TQ1089 Clock Buffer Datasheet

TQ1089 Datasheet, PDF, Equivalent


Part Number

TQ1089

Description

11-Output Configurable Clock Buffer

Manufacture

TriQuint Semiconductor

Total Page 10 Pages
Datasheet
Download TQ1089 Datasheet


TQ1089
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
TQ1089
FBIN GND REFCLK GND GND GND GND
11 10 9 8 7 6 5
TEST 12
VDD 13
Q0 14
GND 15
Q1 16
Q2 17
VDD 18
Phase
Detector
VCO
MUX
Divide Logic
÷2
Output Buffers Group B
Group A
4 VDD
3 Q10
2 Q9
1 GND
28 Q8
27 Q7
26 VDD
19 20
GND Q3
21 22 23
Q4 VDD Q5
24 25
Q6 GND
TriQuint’s TQ1089 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 65 MHz to 90
MHz and from 130 MHz to 180 MHz. The outputs are available at either 1x
and 2x or at 1x and 1/2 x the reference clock frequency, fREF . When one of
the Group A outputs (Q0–Q8) is used as feedback to the PLL, all Group A
outputs will be at fREF , and all Group B outputs (Q9, Q10) will be at 2x fREF
. When one of the Group B outputs is used as feedback to the PLL, all
Group A outputs will be at 1/2 x fREF and all Group B outputs will be at fREF .
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. This completely self-contained PLL requires no external
capacitors or resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a
frequency range from 260 MHz to 360 MHz. By feeding back one of the
output clocks to FBIN, the PLL continuously maintains frequency and
phase synchronization between the reference clock (REFCLK) and each of
the outputs.
11-Output
Configurable
Clock Buffer
Features
• Wide frequency range:
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
eight outputs at fREF
two outputs at 2x fREF or
nine outputs at 1/2 x fREF
one output at fREF
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps + 500 ps (max) or
–350 ps +700 ps (max)
• TTL–compatible with 30 mA
output drive
• 28–pin J–lead surface–mount
package
• Ideal for PowerPC –based
designs
TriQuint’s patented output buffer design delivers a very low output-to-
output skew of 150 ps (max). The TQ1089’s symmetrical TTL outputs are
capable of sourcing and sinking 30 mA.
For additional information and latest specifications, see our website: www.triquint.com
1

TQ1089
TQ1089
Functional Description
The core of the TQ1089 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock
(REFCLK) to the feedback clock (FBIN), maintaining a
zero frequency difference between the two. Since one
of the outputs is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps +500 ps for the
TQ1089–MC500, and within –350 ps +700 ps for the
TQ1089–MC700.
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The test mode is outlined
in Table 2.
The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the TQ1089 are TTL-compatible with 30
mA symmetric drive and a minimum VOH of 2.4 V.
The internal Voltage-Controlled Oscillator (VCO), has an
operating range of 260 MHz to 360 MHz, as shown in
Table 1. The combination of the VCO and the Divide
Logic enables the TQ1089 to operate between 65 MHz
and 90 MHz and from 130 MHz to 180 MHz.
Power Up/Reset Synchronization
After power up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection
Output
Test Feedback Mode
0 Group B ÷ 2
0 Group A ÷ 4
Reference Clock
Frequency Range
130 MHz – 180 MHz
65 MHz – 90 MHz
Output Frequency Range
Group A: Q0–Q8
Group B: Q9,Q10
65 MHz – 90 MHz
65 MHz – 90 MHz
130 MHz – 180 MHz
130 MHz – 180 MHz
Table 2. Test Mode Selection
Test Mode
1 ÷2
Ref. Clock
f REF
Group A
Outputs Q0–Q8
f REF ÷ 4
Group B
Outputs Q9, Q10
f REF ÷ 2␣
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . Figure 1. Block Dia gram FBIN GND REFCLK GND GND GND 11 10 9 8 7 6 TQ1089 GND 5 4 VDD 3 TEST 12 VDD 13 Phase Detector VCO Q10 Q9 11- Output Configurable Clock Buffer Featur es • Wide frequency range: 65 MHz to 90 MHz and 130 MHz to 180 MHz • Outpu t configurations: eight outputs at fREF two outputs at 2x fREF or nine outputs at 1/2 x fREF one output at fREF • L ow output-to-output skew: 150 ps (max) within a group SYSTEM TIMING PRODUCTS Q0 14 2 GND 15 Q1 Q2 16 17 MUX Divi de Logic ÷2 Output Buffers Group B Gro up A 1 GND 28 27 Q8 Q7 VDD 18 26 VD D 19 20 21 22 23 24 25 GND Q3 Q4 VDD Q5 Q6 GND TriQuint’s TQ1 089 is a configurable clock buffer whic h generates 11 outputs, operating over a wide range of frequencies from 65 MHz to 90 MHz and from 130 MHz to 180 MHz. The outputs are available at either 1x and 2x or at 1x and 1/2 x the referenc e clock frequency, fREF . When one of the Group A outputs (Q0–Q8) is use.
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