TQ2059 Clock Generator Datasheet

TQ2059 Datasheet, PDF, Equivalent


Part Number

TQ2059

Description

High-Frequency Clock Generator

Manufacture

TriQuint Semiconductor

Total Page 6 Pages
Datasheet
Download TQ2059 Datasheet


TQ2059
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Pinout Diagram
TQ2059
11 10 9 8 7 6 5
High-Frequency
Clock Generator
VDD 12
NC 13
Phase
Detector
VCO
÷10
MUX
4 NC
3 NC
TEST1 14
TEST2 15
NC 16
Control
÷2
MUX
2 NC
1 NC
28 NC
NC 17
27 NC
GND 18
19
20 21
22 23 24 25
26
AVDD
Features
• Output frequency range:
200 MHz to 350 MHz
• One differential PECL output:
600 mV (min) swing
• Common-mode voltage:
VDD –1.2 V (max),
VDD –1.6 V (min)
• Period-to-period output jitter:
30 ps peak-to-peak (typ)
120 ps peak-to-peak (max)
• Reference clock input:
20 MHz to 35 MHz TTL-level
crystal oscillator
TriQuint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz
to 35 MHz TTL input to generate a 200 MHz to 350 MHz PECL output. The
TQ2059 has a completely self-contained Phase-Locked Loop (PLL) running
at 400 MHz to 700 MHz. This stable PLL allows for a low period-to-period
output jitter of 120 ps (max), and enables tight duty-cycle control of 55%to
45% (worst case).
The TQ2059 provides optional 200-ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
• Self-contained loop filter
• Optional 200-ohm pull-down
resistors for AC-coupled outputs
• +5 V power supply
• 28-pin J-lead surface-mount
package
• Ideal for designs based on DEC
Alpha AXPprocessors
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
For additional information and latest specifications, see our website: www.triquint.com
1

TQ2059
TQ2059
Figure 2. Simplified Block Diagram
REFCLK
(20 MHz to
35 MHz)
Phase
Detector
TESTIN
TEST1
TEST2
Control
VCO
MUX ÷2
÷10
MUX
QN
(200 MHz
to
Q 350 MHz)
Table 1. Mode Selection
Mode
TEST1
TEST2
TESTIN 1
REFCLK 2
1 (Test)
2 (Test)
00
01
fTESTCLK
“don’t care”
“don't care”
“don't care”
3 (Test)
4 (Bypass)
5 (Normal)
10
11
11
fTESTCLK
0
1
“don't care”
fREFCLK
fREFCLK
Note: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown.
2. REFCLK = 20 MHz to 35 MHz.
3. Q, QN = 200 MHz to 350 MHz.
Q, QN
fTESTCLK ÷ 20
0, 1
fTESTCLK ÷ 2
fREFCLK
10 x fREFCLK 3
Recommended Layout
(Not to scale)
Pin 1 VDD
GND
0.1 µF
GND
REFCLK
(fr(oFmroTmTLToTsLciOllastcoirl)lator)
GND
0.1 µF
VDD
Q 50 OHMS
QN
VDD
0.1 µF
GND
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ2059 Figure 1. Pi nout Diagram TESTIN REFCLK 11 10 9 8 7 6 5 4 NC High-Frequency Clock G enerator Features • Output frequency range: 200 MHz to 350 MHz • One diffe rential PECL output: 600 mV (min) swing • Common-mode voltage: VDD –1.2 V (max), VDD –1.6 V (min) • Period-to -period output jitter: 30 ps peak-to-pe ak (typ) 120 ps peak-to-peak (max) SYST EM TIMING PRODUCTS GND GND NC VDD N C TEST1 TEST2 NC NC GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Control MUX Phase Detector VCO NC ÷10 ÷2 NC MUX 3 2 NC NC 1 NC 28 NC 27 NC 26 A VDD AGND EVDD PDR2 QN PDR1 GND Q • R eference clock input: 20 MHz to 35 MHz TTL-level crystal oscillator • Self-c ontained loop filter • Optional 200-o hm pull-down resistors for AC-coupled o utputs • +5 V power supply • 28-pin J-lead surface-mount package • Ideal for designs based on DEC Alpha AXP™ processors TriQuint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz to .
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