Clock Generator. TQ2060 Datasheet


TQ2060 Generator. Datasheet pdf. Equivalent


TQ2060


High-Frequency Clock Generator
T

R

I

Q

U

I

N

T

S E M I C O N D U C T O R, I N C .

Figure 1. Pinout Diagram
TESTIN REFCLK GND GND

TQ2060
9 8 7 6 5 4 NC

11

10

High-Frequency Clock Generator

NC

VDD NC TEST1 TEST2 NC NC GND

12 13 14 15 16 17 18 19 20 21 22 23 24 25
Control MUX Phase Detector VCO

NC

÷10 ÷2

NC

MUX

3 2 1

NC NC NC

Features
• Output frequency range: 350 MHz to 500 MHz • One differential PECL output: 600 mV (min) swing • Common-mode voltage: VDD –1.2 V (max), VDD –1.6 V (min) • Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) • Reference clock input: 35 MHz to 50 MHz TTL-level crystal oscillator • Self-contained loop filter • Optional 200-ohm pull-down resistors for AC-coupled outputs • +5 V power supply • 28-pin J-lead surface-mount package • Ideal for designs based on DEC Alpha AXP™ processors

28 NC 27 NC 26 AVDD

QN

AGND

Q

EVDD

PDR2

PDR1

GND

TriQuint’s TQ2060 is a high-frequency clock generator. It utilizes a 35 MHz to 50 MHz TTL input to generate a 350 MHz to 500 MHz PECL output. The TQ2060 has a completely self-contained Phase-Locked Loop (PLL) running at 700 MHz to 1000 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case). The TQ2060 provides optional 200 ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the ...



TQ2060
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Pinout Diagram
TQ2060
11 10 9 8 7 6 5
High-Frequency
Clock Generator
VDD 12
NC 13
TEST1 14
TEST2 15
NC 16
NC 17
GND 18
Phase
Detector
VCO
÷10
÷2
MUX
Control
4 NC
MUX 3 NC
2 NC
1 NC
28 NC
27 NC
26 AVDD
19 20 21 22 23 24 25
Features
• Output frequency range:
350 MHz to 500 MHz
• One differential PECL output:
600 mV (min) swing
• Common-mode voltage:
VDD –1.2 V (max),
VDD –1.6 V (min)
• Period-to-period output jitter:
25 ps peak-to-peak (typ)
70 ps peak-to-peak (max)
TriQuint’s TQ2060 is a high-frequency clock generator. It utilizes a 35 MHz
to 50 MHz TTL input to generate a 350 MHz to 500 MHz PECL output. The
TQ2060 has a completely self-contained Phase-Locked Loop (PLL) running
at 700 MHz to 1000 MHz. This stable PLL allows for a low period-to-period
output jitter of 70 ps (max), and enables tight duty cycle control of
55% to 45% (worst case).
The TQ2060 provides optional 200 ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
• Reference clock input:
35 MHz to 50 MHz TTL-level
crystal oscillator
• Self-contained loop filter
• Optional 200-ohm pull-down
resistors for AC-coupled outputs
• +5 V power supply
• 28-pin J-lead surface-mount
package
• Ideal for designs based on
DEC Alpha AXPprocessors
For additional information and latest specifications, see our website: www.triquint.com
1

TQ2060
TQ2060
Figure 2. Simplified Block Diagram
REFCLK
(35MHz to
50 MHz)
Phase
Detector
TESTIN
TEST1
TEST2
Control
VCO
MUX ÷ 2
÷ 10
MUX
QN (350 MHz
to
Q 500 MHz)
Table 1. Mode Selection
Mode
TEST1
TEST2
TESTIN 1
REFCLK
1(Test)
2 (Test)
3 (Test)
4 (Bypass)
5 (Normal
00
fTESTCLK
“don’t care”
0
1
“don’t care”
“don't care”
10
11
11
fTESTCLK
0
1
“don't care”
fREFCLK
fREFCLK
Notes: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown.
2. REFCLK = 35 MHz to 50 MHz.
3. Q, QN = 350 MHz to 500 MHz.
Q, QN
fREFCLK2 ÷ 20
0, 1
fTESTCLK ÷ 2
fREFCLK
10 x fREFCLK3
Figure 3. Recommended Layout
(Not to scale)
REFCLK
(from TTLoscillator)
GND
0.1 µF
(From TTL Oscillator)
Pin 1 VDD
GND
0.1 µF
VDD
GND
Q 50 OHMS
QN
VDD
0.1 µF
GND
2 For additional information and latest specifications, see our website: www.triquint.com




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