TQ2060

T R I Q U I N T S E M I C O N D U C T O R, I N C . Figure 1. Pinout Diagram TESTIN REFCLK GND GND TQ2060 9 8 7 6 5 4 NC 11 10 High-Frequency Clock Generator NC VDD NC TEST1 TEST2 NC NC GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Control MUX Phase Detector VCO NC ÷10 ÷2 NC MUX 3 2 1 NC NC NC Features Output frequency range: 350 MHz to 500 MHz One differential PECL output: 600 mV (min) swing Common-mode voltage: VDD –1.2 V (max), VDD –1.6 V (min) Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) Reference clock input: 35 MHz to 50 MHz TTL-level crystal oscillator Self-contained loop filter Optional 200-ohm pull-down resistors for AC-coupled outputs +5 V power supply 28-pin J-lead surface-mount package Ideal for designs based on DEC Alpha AXP™ processors 28 NC 27 NC 26 AVDD QN AGND Q EVDD PDR2 PDR1 GND TriQuint’s TQ2060 is a high-frequency clock generator. It utilizes a 35 MHz to 50 MHz TTL input to generate a 350 MHz to 500 MHz PECL output. The TQ2060 has a completely self-contained Phase-Locked Loop (PLL) running at 700 MHz to 1000 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case). The TQ2060 provides optional 200 ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (Q...