Digital-to-Analog Converter. TQ6122 Datasheet


TQ6122 Converter. Datasheet pdf. Equivalent


Part Number

TQ6122

Description

1 Gigasample/sec/ 8-bit Digital-to-Analog Converter

Manufacture

TriQuint Semiconductor

Total Page 23 Pages
Datasheet
Download TQ6122 Datasheet


TQ6122
TRIQUINT
S E M I C O N D U C T O R, I N C .
BLANK
A0
B0
A4
B4
A5 A6
B5 B6
A7 (MSB)
B7
ECL INPUT
BUFFERS
SELA
MULTIPLEXER
VSS
(-5 V)
DGND
D
CLK +
CLK –
BLANK D0
QBLANK Q0
BLANKING
Q LOGIC
D4 D5 D6 D7 MASTER
Q4 Q5 Q6 Q7 LATCH
BINARY-TO-N-OF-7
SEGMENT ENCODER
(EXT. CONTROL LOOP)
FULL-SCALE ADJUST
BANDGAP
REFERENCE
+ VREF
BLANK D0
QBLANK Q0
D4
S1 S2 S3 S4 S5 S6 S7
SLAVE
Q4 QS1
QS7 LATCH
VOUT
IBLANK I0
VSENSE
I4 IS1
CURRENT-SOURCE ARRAY
IREF
VAA (-5V)
IS7 50
VOUT
50
AGND
BLANK DISABLE
VAA
TriQuint's TQ6122 GIGADAC™ is a monolithic, 8-bit digital-to-analog
converter capable of conversion rates to at least 1000 Megasamples/
second. The TQ6122 DAC may be used for display generation, waveform
and signal synthesis, and video signal reconstruction. The TQ6122 features
a 2:1 data MUX at the input for ease of interface and offers synchronous
blanking capability for maximum ease of use in video applications. It drives
complementary 1 V peak-to-peak swings into 50-ohm loads; on-chip 50-
ohm reverse terminations provide extremely fast settling time.
TQ6122
1 Gigasample/sec,
8-bit Digital-to-Analog
Converter
Features
• 1 Gs/s conversion rate
• 8-bit resolution
• DC differential non-linearity
1/2 LSB (0.2%)
• DC integral non-linearity
1 LSB (0.4%)
• Settling time 2 ns to 0.4% (est.)
• Spurious-free dynamic range
(SFDR) 45 dBc typical
• ECL-compatible inputs
• Synchronous blanking input
• 1.3 W power dissipation
• 44-pin multilayer ceramic
package or unpackaged die
Due to the inherently high speed of TriQuint's one-micron gate
Enhancement / Depletion-mode gallium arsenide process, the TQ6122
offers guaranteed operation at clock rates of 1000 MHz, with typical room
temperature conversion rates of 1.5 Gs/s without multiplexing and 1.3 Gs/s
when using multiplexed inputs. The TQ6122 features output rise and fall
times of 500 ps (10% – 90%), symmetric complementary output transitions,
and glitch impulse values less than 10 pV/sec. When used for sine wave
synthesis, typical spurious and harmonic free dynamic range is 45 dBc.
Applications
• Display generation
• Waveform and signal synthesis
• Video signal reconstruction
The TQ6122 may be retrofitted into designs which currently use TriQuint's
TQ6111, 2, 3, 4M DACs with minimal changes to power supply levels and
input and output connections. The part is available in a 44-pin ceramic
package or as unpackaged die.
For additional information and latest specifications, see our website: www.triquint.com
1

TQ6122
TQ6122
Specifications
Table 1. Absolute Maximum Ratings (1,2)
Symbol
AGND, DGND
VSS
VAA
VO, VO (MAX)
VI (MAX)
II (MAX)
PD
TC
TS
Description
Analog and digital ground
Digital power
Analog power
Analog output (1 V F.S.)
Digital input levels
Digital input currents
Power dissipation
Case backside temperature
Storage temperature
Min
–2
–7
–10
–2.5
VSS –0.5
–1
–65
–65
Typ
Max
+2
+2.5
+0.5
+1
3.0
+135
+150
Notes: 1. Unless otherwise specified: AGND = DGND = 0 V, VSS = VAA = –5 V, VFS = 1 V pk–pk, case temperature = 27 °C.
2. Exceeding the absolute maximum ratings may damage the device. The value shown for a particular
parameter is determined with all other parameters at their nominal values.
Table 2. DC Characteristics (1)
Units
V
V
V
V
V
mA
W
°C
°C
Symbol
Description
Test Conditions
Min. Typ. Max. Unit
VAA
IAA
VSS
ISS
PD
VECLREF
IECLREF
RECLREF
CECLREF
VIH(DC)
VIL(DC)
VCLKH (DC),
VCLKH (DC)
VCLKL (DC),
VCLKL (DC)
IIN
CIN
VOUT (MAX),
VOUT (MAX)
VOUT (MIN),
VOUT (MIN)
Analog supply
VAA current
Digital supply
VSS current
Power dissipation
ECL reference level
ECL ref. input bias current
ECL ref. input resistance
ECL ref. input capacitance
Data input HIGH (ECL)
Data input LOW (ECL)
Clock HIGH input
Note 2
–5.25
VFS = 1 V pk–pk
Note 2
50
–5.5
145
0.9
Note 3, Figure 1
–1.5
Note 3, Figure 1 VECLREF = ±0.2 V –5
Figure 1
DC value (VECLREF = –1.3 V)
DC value (VECLREF = –1.3 V)
Differential clock, Note 4
–1100
VTT
VECLREF +0.3
62
200
1.3
–1.3
0
50
2
–4.75
80
–4.5
265
1.85
–1.1
+5
–500
–1500
–0.7
V
mA
V
mA
W
V
mA
pF
mV
mV
V
Clock LOW input
Differential clock, Note 4
VTT
VECLREF –0.3 V
Data, clock input bias current VIH = –800 mV, VIL = –1800 mV –25
+25 uA
Data, clock input capacitance In multilayer ceramic package
0.5
pF
Maximum absolute output level Note 5
+1 V
Minimum absolute output level Note 5 –1.5 V
(Continued on next page)
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . BLANK B0 A0 B4 A4 B5 A5 B6 A6 B7 A7 (MSB) ECL INPUT B UFFERS MULTIPLEXER TQ6122 1 Gigasample /sec, 8-bit Digital-to-Analog Converter Features SELA V SS (-5 V) DGND D Q BLANKING LOGIC D5 Q5 D6 Q6 D7 Q7 MASTE R LATCH BLANK D0 QBLANK Q0 D4 Q4 CLK CLK + – BLANK D0 D4 Q4 BINARY-TO-N -OF-7 SEGMENT ENCODER S1 S2 S3 S4 S5 S6 S7 QS1 QS7 SLAVE LATCH VOUT VOUT + – V REF I BLANK I0 I4 IS1 IS7 50 50 A GN D CURRENT-SOURCE ARRAY VSENSE IREF V AA (-5V) BLANK DISABLE VAA • 1 Gs/s co nversion rate • 8-bit resolution • DC differential non-linearity 1/ LSB (0 .2%) 2 • DC integral non-linearity 1 LSB (0.4%) MIXED SIGNAL PRODUCTS (EXT. CONTROL LOOP) FULL-SCALE ADJUST QBLAN K Q0 BANDGAP REFERENCE • Settling t ime 2 ns to 0.4% (est.) • Spurious-fr ee dynamic range (SFDR) 45 dBc typical • ECL-compatible inputs • Synchrono us blanking input • 1.3 W power dissi pation • 44-pin multilayer ceramic package or unpackaged die TriQuint's TQ6122 GIGAD.
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