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S E M I C O N D U C T O R, I N C .
TQ8032
64 D0 – 31 Input Buffers 32 x 32 Crosspoint Switch Matrix 64 Output Buffers O0 – 31
800 Megabit/sec 32x32 Digital ECL Crosspoint Switch
CONFIGURE
32 5-Bit Configuration Latches
RESET LOAD IA0 – 4 5
OA0 – 4
5
5:32 Decoder
TQ8032
CNTRL LVL
The TQ8032 is a non-blocking 32 x 32 digital crosspoint switch capable of 800 Megabits per second per port data rates. Utilizing a fully differential internal data path and ECL I/O, the TQ8032 offers a high data rate with exceptional signal fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter and signal skew. The TQ8032 is ideally suited for digital video, data communications and telecommunication switching applications. The non-blocking architecture uses 32 fully independent 32:1 multiplexers (see diagram on page 2), allowing each output port to be independently programmed to any input port. The switch is configured by sequentially loading each multiplexer’s 5-bit program latch (OA0:4) with the desired input port address (IA0:4) and enabling the LOAD pin. When complete, the CONFIGURE pin is strobed and all new configurations are simultaneously transferred into the switch multiplexers. Data integrity is maintained on all unchanged data paths.
Typical output waveform with all channels driven
Features
• >25 Gb/s aggregate BW • 800 Mb/s/port NRZ data rate • Non-blocking architecture • 500 ps delay match • Differential ECL-level data I/O; Selectable CMOS/TTLlevel control inputs • Low jitter and signal skew • Fully differential data path • Double buffered configuration latches • 196-pin CQFP package
Electrical Characteristics
Min
Data Rate/Port Jitter Channel Propagation Delay Ch-to-Ch Propagation Delay Skew 800 150 2300 500
Max
Units
Mb/s ps pk-pk ps ps
Applications
• Telecom/Datacom Switching • Hubs and Routers • Video Switching
For additional information and latest specifications, see our website: www.triquint.com
1
SWITCHING PRODUCTS
32 5-Bit Program Latches
TQ8032
Figure 1. Architecture
32 X 1-BIT MULTIPLEXER
. . . . . .
DATA IN 0 (I0)
32 X 1-BIT MULTIPLEXER
Input Buffers
. . . . . .
DATA IN 15 (I15)
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Output Buffers .
.
. .
DATA OUT 31 (O31) DATA OUT 0 (O0)
DATA IN 16 (I16)
Input Buffers
. . . . . .
DATA IN 31 (I31) CONFIGURE RESET LOAD 5:32 5 DECODE OUTPUT SELECT ADDRESS (OA0:4) Configuration Register Program Register
5
5
INPUT ADDRESS (IA0:4)
Table 2. Pin Descriptions
Signal
I0 to I31, NI0 to NI31 O0 to O31, NO0 to NO31 IA0:4
Name/Level
Data input true and complement. Differential ECL Data output true and complement. Differential ECL Input address. CMOS/TTL
Description
Differential data input ports. Differential data output ports. Input port selection address that is written into the selected output port program latches (OA0:4). IA4 IA3 IA2 IA1 IA0 Input port 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 : : : : : : 1 1 1 1 1 31 Output p.