TQ8106 SONET/SDH Transceivers Datasheet

TQ8106 Datasheet, PDF, Equivalent


Part Number

TQ8106

Description

SONET/SDH Transceivers

Manufacture

TriQuint Semiconductor

Total Page 19 Pages
Datasheet
Download TQ8106 Datasheet


TQ8106
TRIQUINT
S E M I C O N D U C T O R, I N C .
SONET/SDH
Overhead
Processor
Reference
Clock
TQ8105
or
TQ8106
SONET/SDH
Transceiver
Rx O/E
with
CDR
Tx O/E
SONET/SDH
Overhead
Processor
TQ8106
SONET/SDH
Transceiver
with CDR
Rx O/E
Tx O/E
The TQ8105/TQ8106 are SONET/SDH transceivers that integrate
multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and
enhanced line and clock diagnostic functions into a single monolithic device.
The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a
Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow
maximum flexibility in the selection of internal/external Clock and Data
Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.
On-chip PLLs use external RC-based loop filters to allow custom tailoring of
loop response and support the wide range of reference clock frequencies
found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,
the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems
when combined with industry-typical O/E devices such as Sumitomo, AT&T,
HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant-
rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing
clocking for UTOPIA and other system busses. Transmit data may also be
clocked into the devices with respect to the reference clock.
Operating from a single +5V supply, the TQ8105/TQ8106 provides fully
compliant functionality and performance, utilizing direct-connected PECL
levels (differential or single-ended) for high-speed I/O. As compared to AC-
coupled schemes, the direct-coupled connections reduce jitter and
switching-level offsets due to data patterns. The TQ8105/TQ8106 can also
provide direct connection to high-speed I/O utilizing ECL levels with a –5V
supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/
PECL reference clock input is also provided; at 155.52 MHz the input should
be only PECL/ECL.) Output TTL pins can be tristated and may also be
configured for VOH with a 3.3V supply connection.
TQ8105/8106
PRELIMINARY DATA SHEET
SONET/SDH
Transceivers
Features
• Single-chip, byte-wide Mux,
Demux, Framer, and Tx clock-
synthesis PLL with enhanced
diagnostics
• TQ8106 includes monolithic
Clock and Data Recovery
• SONET/SDH/ATM compliant for
STS-12/STM-4 (622 Mb/s) or
STS-3/STM-1 (155 Mb/s) rates
• 155.52, 77.76, 51.84, 38.88, or
19.44 MHz reference clock inputs
with TTL, PECL, or ECL level
• 38.88 MHz and 51.84 MHz clock
outputs for UTOPIA as well as
byte clock rate (77.76 or 19.44 MHz)
• External RC-based loop filters
• Integrated loopbacks with
enhanced line and reference
clock diagnostics
• Direct-coupled standard, PECL,
high-speed I/O with ECL option
• Clean TTL interface to
PMC-Sierra devices
• 100-pin 14x14 mm JEDEC
plastic package
• +5V-only supply for PECL I/O
(–5.2V required for ECL I/O option)
• –40 to +125°C case operating
temperature
For additional information and latest specifications, see our website: www.triquint.com
1

TQ8106
TQ8105/TQ8106
PRELIMINARY DATA SHEET
The combination of a thermally enhanced, 100-pin
JEDEC, metric, plastic package, the low-power
dissipation of the device, and the wide case-
temperature range permits operation without a heat
sink in most designs.
The TQ8106 uses the same pinout as the TQ8105 and
is compatible with it.
The TQ8105/TQ8106 provides comprehensive,
integrated, loopback functionality and enhanced line
and reference clock diagnostics required of SONET/
SDH systems, minimizing additional external circuitry.
Figure 1. TQ8105 Block Diagram
TQ8105/TQ8106 diagnostics include:
• Loss of Reference clock detector (LOR) output to
indicate that the PLL Reference Clock is not toggling
• Lock Indicator (RLOCK), which permits monitoring
of the receiver clock frequency, flagging when the
frequency drifts beyond approximately 500 ppm
• Loss of Signal (LOS) detector output to indicate that
the incoming data stream has no data transitions in
128-bit periods
• ECL/PECL input (NSOL) to allow LOS from an O/E
module to force the data stream to all zeroes,
eliminating the need for external glue logic.
CKSRC(2:0)
TxBC
PH(1:0)
MXD(7:0)
LBM(1:0)
DXD(7:0)
NOE
NRESET
RxBC
FRPWR
LOS
CLRLOS
3
Clock
Phase
2
B
Y
A
Clock/8
PLL Clock
Synthesizer
B
Y
A
Ext. Clk
8
Parallel
to
Serial
2
Clock
Data
8 Hold 11
Register
Serial
to
Parallel
Clock
Data
Loop
Back &
Retime
Block
Clock
Data
/8
Clock
Data
2
ECL/
PECL
I/O
Block
2
2
2
2
Framer
LOS
Detect
Freq.
Lock
Detect
TQ8105
REFCKT
REFCKE
TXCK
TXD
DVPP
VPP
VNN
RXCK
RXD
NSOL
OOF
DXSYNC
RLOCK
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . SONET/SDH Overhead Processor TQ8105 or TQ8106 SONET/SDH T ransceiver Rx O/E with CDR Tx O/E TQ8 105/8106 PRELIMINARY DATA SHEET TELECOM PRODUCTS Reference Clock SONET/SDH T ransceivers Features SONET/SDH Overhea d Processor TQ8106 SONET/SDH Transceiv er with CDR Rx O/E Tx O/E • Single -chip, byte-wide Mux, Demux, Framer, an d Tx clocksynthesis PLL with enhanced d iagnostics • TQ8106 includes monolith ic Clock and Data Recovery • SONET/SD H/ATM compliant for STS-12/STM-4 (622 M b/s) or STS-3/STM-1 (155 Mb/s) rates 155.52, 77.76, 51.84, 38.88, or 19.44 MHz reference clock inputs with TTL, P ECL, or ECL level • 38.88 MHz and 51. 84 MHz clock outputs for UTOPIA as well as byte clock rate (77.76 or 19.44 MHz ) • External RC-based loop filters Integrated loopbacks with enhanced li ne and reference clock diagnostics • Direct-coupled standard, PECL, high-spe ed I/O with ECL option • Clean TTL interface to PMC-Sierra devices • 100-pin 14.
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