Data Demultiplexer. TRCV012G53XE1 Datasheet


TRCV012G53XE1 Demultiplexer. Datasheet pdf. Equivalent


TRCV012G53XE1


TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier/ Clock Recovery/ 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000

TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer

Features
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Applications
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TRCV012G5 supports OC-48/STM-16 data rate TRCV012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate Fully-integrated limiting amplifier, clock recovery, 1:16 data demultiplexer No reference clock required for CDR 2.5 Gbits/s data output and 2.5 GHz recovered clock output available for wavelength division multiplex (WDM) or regenerator applications Programmable limiting amplifier offset Programmable data sampling phase Additional CML serial data input for system loopback Parity bit generation Analog and digital loss of signal (LOS) indicators Optional demultiplexer powerdown mode conserves power Single 3.3 V supply Available in either MBIC 025 BiCMOS technology or lower-power MBIC 025 silicon germanium BiCMOS technology High-speed LVPECL digital I/O Jitter tolerance, transfer, and generation compliant with the following: — Telcordia Technologies* GR-253 — ITU-T G.825 — ITU-T G.958 Loss of signal compliant with the following: — Telcordia Technologies GR-253

SONET/SDH line termination equipment SONET/SDH add/drop multiplexers SONET/SDH cross connects SONET/SDH test equipment

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Description
The Lucent Technologies Microelectro...



TRCV012G53XE1
Preliminary Data Sheet
August 2000
TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Features
s TRCV012G5 supports OC-48/STM-16 data rate
s TRCV012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
s Fully-integrated limiting amplifier, clock recovery,
1:16 data demultiplexer
s No reference clock required for CDR
s 2.5 Gbits/s data output and 2.5 GHz recovered
clock output available for wavelength division
multiplex (WDM) or regenerator applications
s Programmable limiting amplifier offset
s Programmable data sampling phase
s Additional CML serial data input for system
loopback
s Parity bit generation
s Analog and digital loss of signal (LOS) indicators
s Optional demultiplexer powerdown mode
conserves power
s Single 3.3 V supply
s Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
s High-speed LVPECL digital I/O
s Jitter tolerance, transfer, and generation compliant
with the following:
Telcordia Technologies* GR-253
— ITU-T G.825
— ITU-T G.958
s Loss of signal compliant with the following:
Telcordia Technologies GR-253
* Telcordia Technologies is a registered trademark of Bell Com-
munications Research, Inc.
Applications
s SONET/SDH line termination equipment
s SONET/SDH add/drop multiplexers
s SONET/SDH cross connects
s SONET/SDH test equipment
Description
The Lucent Technologies Microelectronics Group
TRCV012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TRCV012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TRCV012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TRCV012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices contain a limiting amplifier with 30 dB
gain, a clock and data recovery PLL with high-speed
serial clock and data outputs, and a 1:16 demulti-
plexer with differential PECL data and clock outputs.
The device provides improved optical receiver perfor-
mance when used in optically amplified systems due
to a direct slice adjust input pin and a 6 ps adjust-
ment capability in the slicing decision time. Both
devices are available in either BiCMOS or in SiGe
BiCMOS technology for lower power operation.

TRCV012G53XE1
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
Table of Contents
Contents
Page
Features .................................................................................................................................................................... 1
Applications ............................................................................................................................................................... 1
Description................................................................................................................................................................. 1
Pin Information ..........................................................................................................................................................4
Functional Overview ................................................................................................................................................10
Limiting Amplifier .....................................................................................................................................................10
Limiting Amplifier Operation..................................................................................................................................10
Clock and Data Recovery (CDR).............................................................................................................................11
Clock Recovery Operation ....................................................................................................................................11
Clock Recovery PLL Loop Filter ...........................................................................................................................11
CDR Acquisition Time...........................................................................................................................................11
CDR Generated Jitter ...........................................................................................................................................11
CDR Input Jitter Tolerance ...................................................................................................................................12
CDR Jitter Transfer ...............................................................................................................................................12
Clock Recovery Jitter Tolerance and Jitter Transfer Specifications......................................................................13
Data Path Configuration Option (ENDATAN) .......................................................................................................14
High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N)....................................................14
High-Speed Serial Data Output Mute (MUTE2G5N) ............................................................................................14
Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN).........................................................14
Decision Circuit—Adjustable Sampling Time (ASTREF, AST[4:0]).........................................................................15
Loss of Signal Detection..........................................................................................................................................16
Digital Loss of Signal (LOSDN).............................................................................................................................16
Analog Loss of Signal (LOSAN, PRG_LOSA) ......................................................................................................16
Demultiplexer Operation..........................................................................................................................................17
Parity Generation (PARITYP/N)............................................................................................................................17
Demultiplexer Powerdown (PDDMXN) .................................................................................................................17
Demultiplexer Data Mute (MUTEDMXN) ..............................................................................................................17
CK155P/N Low-Speed Output Mute (MUTE155N)...............................................................................................17
CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N).................................................................................18
Choosing the Value of the External CML Reference Resistors (RREF1, RREF2) ...............................................18
Absolute Maximum Ratings.....................................................................................................................................19
Handling Precautions ..............................................................................................................................................19
Operating Conditions...............................................................................................................................................19
Electrical Characteristics .........................................................................................................................................20
Limiting Amplifier Specifications ...........................................................................................................................20
Optional Reference Frequency (REFCLKP/N) Specifications ..............................................................................20
LVPECL, CMOS, CML Input and Output Pins ......................................................................................................21
Timing Characteristics .............................................................................................................................................23
Output Timing .......................................................................................................................................................23
Outline Diagram.......................................................................................................................................................25
128-Pin QFP .........................................................................................................................................................25
Board Installation Recommendations ...................................................................................................................26
Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS) .....................................................26
Ordering Information................................................................................................................................................27
DS00-234HSPL Replaces DS00-154HSPL to Incorporate the Following Updates.................................................27
2 Lucent Technologies Inc.




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