TS68EN360 Communication Controller Datasheet

TS68EN360 Datasheet, PDF, Equivalent


Part Number

TS68EN360

Description

32-bitQuad Integrated Communication Controller

Manufacture

ATMEL Corporation

Total Page 30 Pages
Datasheet
Download TS68EN360 Datasheet


TS68EN360
Features
CPU32+ Processor (4.5 MIPS at 25 MHz)
– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)
– Background Debug Mode
– Byte-misaligned Addressing
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0 - 25 MHz Operation)
Slave Mode to Disable CPU32+ (Allows Use with External Processors)
– Multiple QUICCs Can Share One System Bus (One Master)
– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
Intelligent Peripheral (22 MIPS at 25 MHz)
– Peripheral Device of TSPC603e (see DC415/D note)
Four General-purpose Timers
– Superset of MC68302 Timers
– Four 16-bit Timers or Two 32-bit Timers
– Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
Communications Processor Module (CPM)
Four Baud Rate Generators
Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)
Two SMC
VCC = +5V ± 5%
fmax = 25 MHz and 33 MHz
Military Temperature Range: -55°C < TC < +125°C
PD = 1.4 W at 25 MHz; 5.25V
2 W at 33 MHz; 5.25V
32-bit Quad
Integrated
Communication
Controller
TS68EN360
Description
The TS68EN360 QUad Integrated Communication Controller (QUICC) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications activities.
The QUICC (pronounced “quick”) can be described as a next-generation TS68302
with higher performance in all areas of device operation, increased flexibility, major
extensions in capability, and higher integration. The term “quad” comes from the fact
that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management control-
lers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
• MIL-STD-883 (class B)
• QML (class Q)
• or according to Atmel standards
Rev. 2113A–HIREL–03/02
1

TS68EN360
R suffix
PGA 241
Ceramic Pin Grid Array Cavity Up
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier Cavity Down
Introduction
QUICC Architecture
Overview
The QUICC is 32-bit controller that is an extension of other members of the TS68300
family. Like other members of the TS68300 family, the QUICC incorporates the inter-
module bus (IMB). The TS68302 is an exception, having an 68000 bus on chip. The IMB
provides a common interface for all modules of the TS68300 family, which allows the
development of new devices more quickly by using the library of existing modules.
Although the IMB definition always included an option for an on-chip 32-bit bus, the
QUICC is the first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM.
Each module utilizes the 32-bit IMB.
The TS68EN360 QUICC block diagram is shown in Figure 1.
Figure 1. QUICC Block Diagram
CPU32+
CORE
SIM 60
SYSTEM
PROTECTION
JTAG
PERIODIC
TIMER
BREAKPOINT
LOGIC
CLOCK
GENERATION
OTHER
FEATURES
DRAM
CONTROLLER
AND
CHIP SELECTS
IMB (32 BIT)
EXTERNAL
BUS
INTERFACE
SYSTEM
I/F
TWO
IDMAs
CPM
COMMUNICATIONS PROCESSOR
RISC
CONTROLLER
FOURTEEN SERIAL
DMAs
2.5-KBYTE
DUAL-PORT
RAM
INTERRUPT
CONTROLLER
FOUR
GENERAL-
PURPOSE
TIMERS
SEVEN
SERIAL
CHANNELS
TIMER SLOT
ASSIGNER
OTHER
FEATURES
2 TS68EN360
2113A–HIREL–03/02


Features .
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