TN2425 DMOS FETs Datasheet

TN2425 Datasheet, PDF, Equivalent


Part Number

TN2425

Description

N-Channel Enhancement-Mode Vertical DMOS FETs

Manufacture

Supertex Inc

Total Page 5 Pages
Datasheet
Download TN2425 Datasheet


TN2425
Supertex inc.
TN2425
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold
High input impedance
Low input capacitance
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
Packing
TN2425N8-G
TO-243AA (SOT-89)
2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
25V 3.58Ω
Pin Configuration
IDSS
(min)
1.5A
Absolute Maximum Ratings
Parameter
Value
DRAIN
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
SOURCE
DRAIN
GATE
TO-243AA (SOT-89)
Product Marking
Typical Thermal Resistance
Package
θja
TO-243AA (SOT-89)
133OC/W
TN4CW
W = Code for Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-243AA (SOT-89)
Doc.# DSFP-TN2425
B080913
Supertex inc.
www.supertex.com

TN2425
TN2425
Thermal Characteristics
Package
(continIDuous)
ID
(pulsed)
Power Dissipation
@TC = 25OC
IDR
TO-243AA (SOT-89)
480mA
1.90A
1.6W
480mA
Notes:
ID (continuous) is limited by max rated Tj .
TA = 25°C. Mounted on FR5 Board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substrate.
IDRM
1.90A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
250 - - V VGS = 0V, ID = 250µA
VGS(th) Gate threshold voltage
0.8 - 2.5 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- - -5.5 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current
0.8 - - A VGS = 4.5V, VDS = 25V
1.5 -
-
VGS = 10V, VDS = 25V
- - 6.0
VGS = 3.0V, ID = 150mA
RDS(ON) Static drain-to-source on-state resistance
-
- 5.0 Ω VGS = 4.5V, ID = 250mA
- - 3.5
VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature
- - 1.7 %/OC VGS = 10V, ID = 500mA
GFS Forward transductance
500 -
- mmho VDS = 25V, ID = 250mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 105 200
VGS = 0V,
- 25 100 pF VDS = 25V,
- 7.0 40
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- 5.0 15
- 10 25
- 25 35
- 5.0 15
VDD = 25V,
ns ID = 500mA,
RGEN = 25Ω
VSD Diode forward voltage drop
- - 1.5 V VGS = 0V, ISD = 500mA
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
td(ON)
tr
90%
t(OFF)
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Doc.# DSFP-TN2425
B080913
2
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Supertex inc.
www.supertex.com


Features Supertex inc. TN2425 N-Channel Enhance ment-Mode Vertical DMOS FET Features ► Low threshold ►► High input i mpedance ►► Low input capacitance ► Fast switching speeds ►► Low on-resistance ►► Free from secondar y breakdown ►► Low input and output leakage Applications ►► Logic leve l interfaces – ideal for TTL and CMOS ►► Solid state relays ►► Batte ry operated systems ►► Photo voltai c drives ►► Analog switches ►► General purpose line drivers ►► Tel ecom switches General Description This low threshold, enhancement-mode (norma lly-off) transistor utilizes a vertical DMOS structure and Supertex’s well-p roven, silicon-gate manufacturing proce ss. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperatur e coefficient inherent in MOS devices. Characteristic of all MOS structures, t his device is free from thermal runaway and thermally-induced s.
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