TN2524 DMOS FETs Datasheet

TN2524 Datasheet, PDF, Equivalent


Part Number

TN2524

Description

N-Channel Enhancement-Mode Vertical DMOS FETs

Manufacture

Supertex Inc

Total Page 5 Pages
Datasheet
Download TN2524 Datasheet


TN2524
Supertex inc.
TN2524
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold (2.0V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
Packing
TN2524N8-G
TO-243AA (SOT-89)
2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
240V
6.0Ω
Pin Configuration
ID(ON)
(min)
1.0A
VGS(TH)
(max)
2.0V
Absolute Maximum Ratings
Parameter
Value
DRAIN
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
SOURCE
DRAIN
GATE
TO-243AA (SOT-89)
Product Marking
Typical Thermal Resistance
Package
θja
TO-243AA (SOT-89)
133OC/W
TN5CW
W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-243AA (SOT-89)
Doc.# DSFP-TN2524
C080913
Supertex inc.
www.supertex.com

TN2524
TN2524
Thermal Characteristics
Package
(continIDuous)
ID
(pulsed)
TO-243AA (SOT-89)
360mA
2.0A
Notes:
ID (continuous) is limited by max rated Tj .
TA = 25°C. Mounted on FR5 Board, 25mm x 25mm x 1.57mm.
Power Dissipation
@TC = 25OC
1.6W
IDR
360mA
IDRM
2.0A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
240 - - V VGS = 0V, ID = 2.0mA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- - -5.0 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
0.5 1.9
1.0 2.8
-
-
A VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance
- 4.0 6.0
- 4.0 6.0
Ω VGS = 4.5V, ID = 250mA
VGS = 10, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature
- - 1.4 %/OC VGS = 10V, ID = 500mA
GFS Forward transductance
300 600
- mmho VDS = 25V, ID = 500mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 65 125
VGS = 0V,
- 35 70 pF VDS = 25V,
- 10 25
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- - 10
- - 10
VDD = 25V,
-
-
20
ns ID = 1.0A,
RGEN = 25Ω
- - 20
VSD Diode forward voltage drop
- - 1.8 V VGS = 0V, ISD = 1.0A
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Doc.# DSFP-TN2524
C080913
Supertex inc.
2 www.supertex.com


Features Supertex inc. TN2524 N-Channel Enhance ment-Mode Vertical DMOS FET Features ► Low threshold (2.0V max.) ►► High input impedance ►► Low input c apacitance (125pF max.) ►► Fast swi tching speeds ►► Low on-resistance ►► Free from secondary breakdown ► Low input and output leakage Appli cations ►► Logic level interfaces ideal for TTL and CMOS ►► Solid state relays ►► Battery operated sy stems ►► Photo voltaic drives ► Analog switches ►► General purpos e line drivers ►► Telecom switches General Description This low threshold , enhancement-mode (normally-off) trans istor utilizes a vertical DMOS structur e and Supertex’s well-proven, silicon -gate manufacturing process. This combi nation produces a device with the power handling capabilities of bipolar trans istors and with the high input impedanc e and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runawa.
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