DMOS FETs. TN2540 Datasheet


TN2540 FETs. Datasheet pdf. Equivalent


TN2540


N-Channel Enhancement-Mode Vertical DMOS FETs
Supertex inc.

TN2540

N-Channel Enhancement-Mode

Vertical DMOS FET

Features

General Description

►► Low threshold (2.0V max.) ►► High input impedance ►► Low input capacitance (125pF max.) ►► Fast switching speeds ►► Low on-resistance ►► Free from secondary breakdown ►► Low input and output leakage
Applications

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

►► Logic level interfaces - ideal for TTL and CMOS ►► Solid state relays ►► Battery operated systems ►► Photo voltaic drives ►► Analog and Telecom switches ►►...



TN2540
Supertex inc.
TN2540
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
General Description
Low threshold (2.0V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog and Telecom switches
General purpose line drivers
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Part Number
Package Options Packing
TN2540N3-G
TO-92
1000/Bag
TN2540N3-G P002 TO-92
2000/Reel
TN2540N3-G P003 TO-92
2000/Reel
TN2540N3-G P005 TO-92
2000/Reel
TN2540N3-G P013 TO-92
2000/Reel
TN2540N3-G P014 TO-92
2000/Reel
TN2540N8-G
TO-243AA (SOT-89) 2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package
Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014 TO-92
Taping Specifications and Winding Styles
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
θja
TO-92
132OC/W
TO-243AA (SOT-89)
133OC/W*
* Mounted on FR5 Board, 25mm x 25mm x 1.57mm
Doc.# DSFP-TN2540
A062113
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
400V
12Ω
ID(ON)
(min)
1.0A
VGS(th)
(max)
2.0V
Pin Configuration
DRAIN
SOURCE
DRAIN
GATE
TO-92
SOURCE
DRAIN
GATE
TO-243AA (SOT-89)
Product Marking
SiTN
2540
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
TN5DW
W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-243AA (SOT-89)
Supertex inc.
www.supertex.com

TN2540
TN2540
Thermal Characteristics
Package
ID
(continuous)
ID
(pulsed)
Power Dissipation
@TA = 25OC
IDR
IDRM
TO-92
175mA
TO-243AA (SOT-89)
260mA
Notes:
IMD o(cuonntetidnuoonuFs)Ri5s
limited
Board,
b2y5mmmaxxra2t5emdmTj
.
x
1.57mm.
2.0A
1.8A
1.0W
1.6W
175mA
260mA
2.0A
1.8A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
400 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- -2.5 -4.0 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
0.3 0.5
0.75 1.0
-
-
A VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance
- 8.0 12
- 8.0 12
Ω VGS = 4.5V, ID = 150mA
VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature
- - 0.75 %/OC VGS = 10V, ID = 500mA
GFS Forward transductance
125 200
- mmho VDS = 25V, ID = 100mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 95 125
VGS = 0V,
- 20 70 pF VDS = 25V,
- 10 25
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- - 20
-
-
-
-
-
-
15
25
20
VDD = 25V,
ns ID = 1.0A,
RGEN = 25Ω
VSD Diode forward voltage drop
- - 1.8 V VGS = 0V, ISD = 200mA
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V 90%
INPUT
0V
10%
t(ON)
t(OFF)
td(ON)
tr
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Doc.# DSFP-TN2540
A062113
2
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Supertex inc.
www.supertex.com




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