TN5325 DMOS FETs Datasheet

TN5325 Datasheet, PDF, Equivalent


Part Number

TN5325

Description

N-Channel Enhancement-Mode Vertical DMOS FETs

Manufacture

Supertex Inc

Total Page 6 Pages
Datasheet
Download TN5325 Datasheet


TN5325
TN5325
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold (2.0V max.)
High input impedance and high gain
Free from secondary breakdown
Low CISS and fast switching speeds
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Device
Package Options
TO-236AB (SOT-23)
TO-92
TO-243AA (SOT-89)
TN5325
TN5325K1-G
-G indicates package is RoHS compliant (‘Green’)
TN5325N3-G
TN5325N8-G
BVDSS/BVDGS
(V)
250
RDS(ON)
(max)
(Ω)
7.0
ID(ON)
(min)
(A)
1.2
VGS(th)
(max)
(V)
2.0
Pin Configurations
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Soldering temperature*
300OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
DRAIN
SOURCE
GATE
TO-236AB (SOT-23) (K1)
DRAIN
DRAIN
SOURCE
GATE
TO-92 (N3)
SOURCE
DRAIN
GATE
TO-243AA (SOT-89) (N8)
Product Marking
N3CW
W = Code for week sealed
= “Green” Packaging
TO-236AB (SOT-23) (K1)
SiTN YY = Year Sealed
5 3 2 5 WW = Week Sealed
YYWW
= “Green” Packaging
TO-92 (N3)
TN3CW W = Code for week sealed
= “Green” Packaging
TO-243AA (SOT-89) (N8)
Packages may or may not include the following marks: Si or
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

TN5325
TN5325
Thermal Characteristics
Package
(continIDuous)
(mA)
ID
(pulsed)
(A)
TO-236AB (SOT-23) 150 0.4
TO-92
215 0.8
TO-243AA (SOT-89)
316
Notes:
MID o(cuonntetidnuoonuFs)Ri5s
limited
Board,
b2y5mmmaxxra2t5emdmTj
.
x
1.57mm.
1.5
Power Dissipation
@TA = 25OC
(W)
0.36
0.74
1.6
θjc
(OC/W)
200
125
15
θja
(OC/W)
350
170
78
IDR
(mA)
150
215
316
IDRM
(A)
0.4
0.8
1.5
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
250 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID = 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- - -4.5 mV/OC VGS = VDS, ID = 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 1.0 µA VGS = 0V, VDS = 100V
- - 10
VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
0.6 - - A VGS = 4.5V, VDS = 25V
1.2 -
-
VGS = 10V, VDS = 25V
RDS(ON)
Static drain-to-source
on-state resistance
- - 8.0 Ω VGS = 4.5V, ID = 150mA
- - 7.0
VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature
- - 1.0 %/OC VGS = 4.5V, ID = 150mA
GFS Forward transductance
150 -
- mmho VDS = 25V, ID = 200mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- - 110
VGS = 0V,
- - 60 pF VDS = 25V,
- - 23
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- - 20
- - 15
VDD = 25V,
-
-
25
ns ID = 150mA,
RGEN = 25Ω
- - 25
VSD Diode forward voltage drop
- - 1.8 V VGS = 0V, ISD = 200mA
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 200mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
2


Features TN5325 N-Channel Enhancement-Mode Verti cal DMOS FET Features ► Low threshol d (2.0V max.) ► High input impedance and high gain ► Free from secondary b reakdown ► Low CISS and fast switchin g speeds Applications ► Logic level i nterfaces - ideal for TTL and CMOS ► Solid state relays ► Battery operated systems ► Photo voltaic drives ► A nalog switches ► General purpose line drivers ► Telecom switches General Description This low threshold, enhance ment-mode (normally-off) transistor uti lizes a vertical DMOS structure and Sup ertex’s well-proven, silicon-gate man ufacturing process. This combination pr oduces a device with the power handling capabilities of bipolar transistors an d the high input impedance and positive temperature coefficient inherent in M OS devices. Characteristic of all MOS s tructures, this device is free from the rmal runaway and thermally-induced seco ndary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and a.
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