TN5335 DMOS FETs Datasheet

TN5335 Datasheet, PDF, Equivalent


Part Number

TN5335

Description

N-Channel Enhancement-Mode Vertical DMOS FETs

Manufacture

Supertex Inc

Total Page 5 Pages
Datasheet
Download TN5335 Datasheet


TN5335
Supertex inc.
TN5335
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold
High input impedance
Low input capacitance
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Product Summary
Part Number
TN5335K1-G
TN5335N8-G
Package Option
TO-236AB (SOT-23)
TO-243AA (SOT-89)
Packing
3000/Reel
2000/Reel
BVDSS/BVDGS
350V
RDS(ON)
(max)
15Ω
ID(ON)
(min)
750mA
VGS(th)
(max)
2.0V
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Pin Configuration
Absolute Maximum Ratings
DRAIN
DRAIN
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Value
BVDSS
BVDGS
±20V
-55OC to +150OC
SOURCE
GATE
TO-236AB (SOT-23)
SOURCE
DRAIN
GATE
TO-243AA (SOT-89)
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Product Marking
N3SW
W = Code for week sealed
= “Green” Packaging
Typical Thermal Resistance
Package
TO-236AB (SOT-23)
θja
203OC/W
TO-243AA (SOT-89)
173OC/W
Package may or may not include the following marks: Si or
TO-236AB (SOT-23)
TN3SW W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-243AA (SOT-89)
Doc.# DSFP-TN5335
B081213
Supertex inc.
www.supertex.com

TN5335
Thermal Characteristics
Package
(continIDuous)
TO-236AB (SOT-23)
110mA
TO-243AA (SOT-89)
230mA
Notes:
MID o(cuonntetidnuoonuFs)Ri5s
limited
Board,
b2y5mmmaxxra2t5emdmTj
.
x
1.57mm.
ID
(pulsed)
0.8A
1.3A
Power Dissipation
@TA = 25OC
0.36W
1.6W
IDR
110mA
230mA
TN5335
IDRM
0.8A
1.3A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
350 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- - -4.5 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 1.0 µA VGS = 0V, VDS = 100V
- - 10
VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
300 -
750 -
- mA VGS = 4.5V, VDS = 25V
- VGS = 10V, VDS = 25V
- - 15
VGS = 3.0V, ID = 20mA
RDS(ON) Static drain-to-source on-state resistance -
- 15
Ω VGS = 4.5V, ID = 150mA
- - 15
VGS = 10V, ID = 200mA
ΔRDS(ON) Change in RDS(ON) with temperature
- - 1.0 %/OC VGS = 4.5V, ID = 150mA
GFS Forward transductance
125 -
- mmho VDS = 25V, ID = 200mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- - 110
VGS = 0V,
- - 60 pF VDS = 25V,
- - 22
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- - 20
- - 15
VDD = 25V,
-
-
25
ns ID = 150mA,
RGEN = 25Ω
- - 25
VSD Diode forward voltage drop
- - 1.8 V VGS = 0V, ISD = 200mA
trr Reverse recovery time
- 800 -
ns VGS = 0V, ISD = 200mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Doc.# DSFP-TN5335
B081213
Supertex inc.
2 www.supertex.com


Features Supertex inc. TN5335 N-Channel Enhance ment-Mode Vertical DMOS FET Features ► Low threshold ►► High input i mpedance ►► Low input capacitance ► Fast switching speeds ►► Low on-resistance ►► Free from secondar y breakdown ►► Low input and output leakage ►► Complementary N- and P- channel devices Applications ►► Log ic level interfaces - ideal for TTL and CMOS ►► Solid state relays ►► Battery operated systems ►► Photo v oltaic drives ►► Analog switches ► General purpose line drivers ► Telecom switches General Description This low threshold, enhancement-mode ( normally-off) transistor utilizes a ver tical DMOS structure and Supertex’s w ell-proven, silicon-gate manufacturing process. This combination produces a de vice with the power handling capabiliti es of bipolar transistors and the high input impedance and positive temperatur e coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from .
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