TMUX03155

Preliminary Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Features I Applications I I I I I Multiplexes three STS-1 signals into a SONET STS-3 signal. Multiplexes three AU-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction. Demultiplexes three STS-1 signals from a SONET STS-3 signal. Demultiplexes three AU-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction. High-speed microprocessor interface configurable to operate with most commercial microprocessors. Detects STS-3/STM-1 (AU-4) loss-of-signal (LOS) conditions. Detects STS-3/STM-1 (AU-4) out-of-frame and loss-of-frame (OOF/LOF) conditions. Provides an 8-bit bus interface at the STS-1/AU-3 rate. Provides a bit serial, nibble-wide, or byte-wide interface at STS-3/STM-1 (AU-4) rate. Provides STS-3/STM-1 (AU-4) selectable scrambler/descrambler functions and B1/B2/B3 generation/detection. Accepts bit rate, nibble rate, or byte rate highspeed clocks (155.52 MHz, 38.88 MHz, or 19.44 MHz, respectively). STS-3/STM-1 (AU-4) internal clock and data recovery. Meets type B jitter tolerance of ITU-T G.958. Accommodates 0.5 UI jitter up to 20 MHz. 155.52 MHz input reference clock for on-chip PLL. Has on-chip PLL for clock synthesis, requiring only one external resistor. No output clock drift in absence of data transitions once lock is acquired. STS-1 termination mode. –40 °C to +85 °C temperature range. 208-pin, shrink quad flat pack (SQFP) package. Complies with GR-253-CO...