I2C-bus controlled PAL/NTSC TV processor
INTEGRATED CIRCUITS
DATA SHEET
TDA8366 I2C-bus controlled PAL/NTSC TV processor
Objective specification File under Inte...
Description
INTEGRATED CIRCUITS
DATA SHEET
TDA8366 I2C-bus controlled PAL/NTSC TV processor
Objective specification File under Integrated Circuits, IC02 January 1995
Philips Semiconductors
Philips Semiconductors
Objective specification
I2C-bus controlled PAL/NTSC TV processor
FEATURES Multistandard vision IF circuit (positive and negative modulation) Video identification circuit in the IF circuit which is independent of the synchronization for stable On Screen Display (OSD) under ‘no-signal’ conditions Source selection with 2 Colour Video Blanking Synchronization (CVBS) inputs and a Y/C (or extra CVBS) input Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor Integrated chrominance trap and bandpass filters (automatically calibrated) Integrated luminance delay line Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function PAL/NTSC colour decoder with automatic search system Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications RGB control circuit with black-current stabilization and white point adjustment; to obtain a good grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment Linear RGB inputs and fast blanking Horizontal synchronization with two control loops and alignment-free horizontal oscillator Vertical count-down circuit Geometry correction by means of modulation of the vertical and EW drive I2...
Similar Datasheet