8-bit microcontroller. P80C557E4 Datasheet

P80C557E4 microcontroller. Datasheet pdf. Equivalent

P80C557E4 Datasheet
Recommendation P80C557E4 Datasheet
Part P80C557E4
Description Single-chip 8-bit microcontroller
Feature P80C557E4; INTEGRATED CIRCUITS P83C557E4/P80C557E4/P89C557E4 Single-chip 8-bit microcontroller Product specifi.
Manufacture NXP
Datasheet
Download P80C557E4 Datasheet




NXP P80C557E4
INTEGRATED CIRCUITS
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
Product specification
Supersedes data of 1999 Feb 15
1999 Mar 02
Philips
Semiconductors



NXP P80C557E4
Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
P83C557E4/P80C557E4/P89C557E4
1. FEATURES
80C51 central processing unit
32 K × 8 ROM respectively FEEPROM (Flash-EEPROM),
expandable externally to 64 Kbytes
ROM/FEEPROM Code protection
1024 × 8 RAM, expandable externally to 64 Kbytes
Two standard 16-bit timer/counters
An additional 16-bit timer/counter coupled to four capture
registers and three compare registers
A 10-bit ADC with eight multiplexed analog inputs and
programmable autoscan
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I2C-bus serial I/O port with byte oriented master and slave
functions
Full-duplex UART compatible with the standard 80C51
On-chip watchdog timer
15 interrupt sources with 2 priority levels (2 to 6 external sources
possible)
Extended temperature range (–40 to +85°C)
4.5 to 5.5 V supply voltage range
Frequency range for 80C51-family standard oscillator:
3.5 MHz to 16 MHz
PLL oscillator with 32 kHz reference and software-selectable
system clock frequency
Seconds Timer
Software enable/disable of ALE output pulse
Electromagnetic compatibility improvements
Wake-up from Power-down by external or seconds interrupt
2. GENERAL DESCRIPTION
The P80C557E4/P83C557E4/P89C557E4 (hereafter generically
referred to as P8xC557E4) single-chip 8-bit microcontroller is
manufactured in an advanced CMOS process and is a derivative of
the 80C51 microcontroller family. The P8xC557E4 has the same
instruction set as the 80C51. Three versions of the derivative exist:
P83C557E4 — 32 Kbytes mask programmable ROM
P80C557E4 — ROMless version of the P83C557E4
P89C557E4 — 32 Kbytes FEEPROM (Flash-EEPROM)
The P8xC557E4 contains a non-volatile 32 Kbytes mask
programmable ROM (P83C557E4) or electrically erasable
FEEPROM respectively (P89C557E4), a volatile 1024 × 8 read/write
data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2C-bus), a “watchdog” timer, an on-chip
oscillator and timing circuits. For systems that require extra
capability the P8xC557E4 can be expanded using standard TTL
compatible memories and logic.
In addition, the P8xC557E4 has two software selectable modes of
power reduction — Idle Mode and power-down mode. The Idle
Mode freezes the CPU while allowing the RAM, timers, serial ports,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic as well as bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system
clock, 58% of the instructions are executed in 0.75 µs and 40% in
1.5 µs. Multiply and divide instructions require 3 µs.
1999 Mar 02
2



NXP P80C557E4
Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
P83C557E4/P80C557E4/P89C557E4
3. ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PACKAGE
NAME DESCRIPTION
ROMless
P80C557E4EBB
QFP80 Plastic Quad Flat Pack; 80 leads
P80C557E4EFB
QFP80 Plastic Quad Flat Pack; 80 leads
ROM coded
P83C557E4EBB/YYY1
P83C557E4EFB/YYY1
QFP80 Plastic Quad Flat Pack; 80 leads
QFP80 Plastic Quad Flat Pack; 80 leads
FEEPROM
P89C557E4EBB
QFP80 Plastic Quad Flat Pack; 80 leads
P89C557E4EFB
QFP80 Plastic Quad Flat Pack; 80 leads
NOTE:
1. YYY denotes the ROM code number
CODE
FREQUENCY RANGE TEMPERATURE
(MHz)
RANGE (°C)
SOT318-1
SOT318-1
3.5 to 16
3.5 to 16
0 to +70
–40 to +85
SOT318-1
SOT318-1
3.5 to 16
3.5 to 16
0 to +70
–40 to +85
SOT318-1
SOT318-1
3.5 to 16
3.5 to 16
0 to +70
–40 to +85
T0 T1
33
INT0 INT1
33
VDD
VSS
PWM0
PWM1
AVSS AVREF ADC0-7 SDA
+–
AVDD ADEXS
5
SCL
SELXTAL1
RSTIN
XTAL1
XTAL2
EA
ALE
PSEN
3 WR
3 RD
0
AD0-7
2
A8-15
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
6
PROGRAM
MEMORY
32 K x 8 ROM
/FEEPROM,
7
1Kx8
boot ROM
DATA
MEMORY
256 x 8 RAM
+
768 x 8 RAM
DUAL
PWM
ADC
I2C
SERIAL
I/O
8-BIT INTERNAL BUS
8-BIT
PORTS
FOUR
16-BIT
CAPTURE
LATCHES
T2
16 16-BIT
TIMER/
EVENT
COUNT-
ERS
T2
16 16-BIT
COMPARA-
TORS
WITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCH–
DOG
TIMER
PLL
oscillator
+
”seconds”
timer
33
P0 P1 P2 P3 TxD RxD
P5 P4
1
CT0I-CT3I
11
T2 RT2
4
CCMMSTR00,-CCMMTS1R5RSTOUTEW XTAL3 XTAL4
0 ALTERNATE FUNCTION OF PORT0
1 ALTERNATE FUNCTION OF PORT1
2 ALTERNATE FUNCTION OF PORT2
3 ALTERNATE FUNCTION OF PORT 3
4 ALTERNATE FUNCTION OF PORT 4
5 ALTERNATE FUNCTION OF PORT 5
6 NOT PRESENT IN P80C557E4
7 ONLY PRESENT IN P89C557E4
Figure 1. Block diagram P8xC557E4
1999 Mar 02
3







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