quadrature transceiver. TDA8779 Datasheet

TDA8779 transceiver. Datasheet pdf. Equivalent

Part TDA8779
Description 10-bit converter interface ADC/DAC for quadrature transceiver
Feature INTEGRATED CIRCUITS DATA SHEET TDA8779 10-bit converter interface (ADC/DAC) for quadrature transce.
Manufacture NXP
Datasheet
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TDA8779
INTEGRATED CIRCUITS
DATA SHEET
TDA8779
10-bit converter interface
(ADC/DAC) for quadrature
transceiver
Objective specification
Supersedes data of 1996 Sep 05
File under Integrated Circuits, IC02
1996 Sep 18



TDA8779
Philips Semiconductors
10-bit converter interface (ADC/DAC) for
quadrature transceiver
Objective specification
TDA8779
FEATURES
Two 10-bit ADCs with multiplexed outputs
Two 10-bit DACs with multiplexed inputs
Sampling rate for the ADCs and DACs up to 20 MHz
Digital outputs (for the ADC) and inputs (for the DAC)
are TTL/CMOS compatible (2.7 to 5.5 V)
Internal reference voltage regulator
Power dissipation 520 mW
Standby mode.
APPLICATIONS
Wireless communication.
GENERAL DESCRIPTION
The TDA8779 contains two 10-bit high speed ADCs and
two 10-bit DACs for wireless communication (for use in
transceiver modules). This device converts two analog
input signals (channels I and Q) and digital inputs
(D0 to D9) at a maximum sampling rate of 20 MHz.
The input bias voltages for the analog input voltages are
provided internally at the middle code. The analog input
and output voltages are AC coupled.
The data sampling is performed on the rising edge of the
clock for ADCs and DACs.
All reference voltages are generated internally.
QUICK REFERENCE DATA
SYMBOL
VCCA1
VCCD1
VCCA2
VCCD2
VCCO
ICCA
ICCD
ICCO
fCLK(ADC)max
INLA
DNLA
fCLK(DAC)max
INLD
DNLD
Ptot
PARAMETER
analog supply voltage for the
ADC part
digital supply voltage for the
ADC part
analog supply voltage for the
DAC part
digital supply voltage for the
DAC part
output stage supply voltage
analog supply current
digital supply current
output stage supply current
maximum clock frequency for
the ADC part
integral non linearity for the
ADC part
differential non linearity for
the ADC part
maximum clock frequency for
the DAC part
integral non linearity for the
DAC part
differential non linearity for
the DAC part
total power dissipation
CONDITIONS
ramp input; fCLK = 20 MHz
full-scale; ramp input;
fCLK = 20 MHz
50% full-scale; ramp input;
fCLK = 20 MHz
full-scale; ramp input;
fCLK = 20 MHz
full-scale; ramp input;
fCLK = 20 MHz
MIN. TYP. MAX. UNIT
4.75 5.0 5.5 V
4.75 5.0 5.5 V
4.75 5.0 5.5 V
4.75 5.0 5.5 V
2.7 3.0 5.5 V
71 mA
31 mA
2 mA
20 − − MHz
− ±2 LSB
− ±0.3 LSB
20 − − MHz
− ±2 LSB
− ±0.75 LSB
520 mW
1996 Sep 18
2





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