analog-to-digital converter. TDA8790 Datasheet

TDA8790 converter. Datasheet pdf. Equivalent

Part TDA8790
Description 8-bit/ 40 Msps 2.7 to 5.5 V universal analog-to-digital converter
Feature INTEGRATED CIRCUITS DATA SHEET TDA8790 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital con.
Manufacture NXP
Datasheet
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INTEGRATED CIRCUITS DATA SHEET TDA8790 8-bit, 40 Msps 2.7 TDA8790 Datasheet
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TDA8790
INTEGRATED CIRCUITS
DATA SHEET
TDA8790
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
Supersedes data of 1995 May 08
File under Integrated Circuits, IC02
1996 Feb 21



TDA8790
Philips Semiconductors
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
TDA8790
FEATURES
8-bit resolution
Operation between 2.7 and 5.5 V
Sampling rate up to 40 MHz
DC sampling allowed
High signal-to-noise ratio over a large analog input
frequency range (7.3 effective bits at 4.43 MHz
full-scale input at fclk = 40 MHz)
CMOS/TTL compatible digital inputs and outputs
External reference voltage regulator
Power dissipation only 30 mW (typical)
Low analog input capacitance, no buffer amplifier
required
Sleep mode (4 mW)
No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
Video data digitizing
Camera
Camcorder
Radio communication.
GENERAL DESCRIPTION
The TDA8790 is an 8-bit universal analog-to-digital
converter (ADC) for video and general purpose
applications. It converts the analog input signal from
2.7 to 5.5 V into 8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz. All digital inputs and
outputs are CMOS/TTL compatible. A sleep mode allows
reduction of the device power consumption down to 4 mW.
QUICK REFERENCE DATA
SYMBOL
VDDA
VDDD
VDDO
VDD
IDDA
IDDD
IDDO
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
supply voltage difference
VDDA VDDD
VDDD VDDO
analog supply current
digital supply current
output stages supply current
INL
DNL
fclk(max)
Ptot
integral non-linearity
differential non-linearity
maximum clock frequency
total power dissipation
CONDITIONS
fclk = 40 MHz; CL = 20 pF;
ramp input
fclk = 40 MHz; ramp input
fclk = 40 MHz; ramp input
VDDA = VDDD = VDDO = 3.3 V
MIN.
2.7
2.7
2.5
TYP.
3.3
3.3
3.3
MAX.
5.5
5.5
5.5
UNIT
V
V
V
0.2
0.2
4
5
1
+0.2
+2.25
6
8
2
V
V
mA
mA
mA
− ±0.5 ±0.75 LSB
− ±0.25 ±0.5 LSB
40 − − MHz
30 53 mW
ORDERING INFORMATION
TYPE
NUMBER
TDA8790M
NAME
SSOP20
PACKAGE
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
VERSION
SOT266-1
1996 Feb 21
2





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