with DPGA. TDA8798 Datasheet

TDA8798 DPGA. Datasheet pdf. Equivalent

Part TDA8798
Description Dual 8-bit/ 100 Msps A/D converter with DPGA
Feature INTEGRATED CIRCUITS DATA SHEET TDA8798 Dual 8-bit, 100 Msps A/D converter with DPGA Objective spec.
Manufacture NXP
Datasheet
Download TDA8798 Datasheet

INTEGRATED CIRCUITS DATA SHEET TDA8798 Dual 8-bit, 100 Msp TDA8798 Datasheet
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TDA8798
INTEGRATED CIRCUITS
DATA SHEET
TDA8798
Dual 8-bit, 100 Msps A/D converter
with DPGA
Objective specification
Supersedes data of 1998 Apr 15
File under Integrated Circuits, IC02
1999 Sep 16



TDA8798
Philips Semiconductors
Dual 8-bit, 100 Msps A/D converter with
DPGA
Objective specification
TDA8798
FEATURES
Dual 8-bit Analog-to-Digital Converter (ADC)
Sampling rate up to 100 million samples per
second (Msps)
Dual 34 dBV 6-bit Digitally Programmable Gain
Amplifier (DPGA) with optional power-off
Optional external equalization filter with capacitive
coupling between DPGA and ADC
Serial Interface (SI) for DPGA gain control using either
parallel load mode or count-up/count-down mode
3.3 V TTL/CMOS compatible I/O
Differential or single-ended TTL/CMOS clock interface
AC or DC coupling for DPGA inputs.
APPLICATIONS
High-dynamic range acquisition front-ends
Digital data storage read channels.
GENERAL DESCRIPTION
The TDA8798 is a dual 8-bit ADC with DPGA.
The 100 Msps maximum sampling rate and 34 dBV DPGA
gain range optimizes the ADC for high dynamic range
applications.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
VDDA
VDDD
VDDO
IDDA
analog supply voltage
digital supply voltage
output stage supply voltage
analog supply current
with DPGAEN LOW
with DPGAEN HIGH
IDDD
IDDO
INL
digital supply current
output stage supply current
DC integral non-linearity
from IC analog input to digital
output; ramp input;
fCLK = 100 MHz
with DPGA at G(min)
without DPGA
DNL
DC differential non-linearity
from IC analog input to digital
output; ramp input;
fCLK = 100 MHz
with DPGA at G(min)
without DPGA
Vn(o)(rms)
output referred noise (RMS value) DPGA at G(max); Zi = 50 ;
noise bandwidth = 15 MHz
B(3dB)(ADC)
B(3dB)(DPGA)
f(sample)(max)
Ptot
ADC 3 dB analogue bandwidth
DPGA 3 dB bandwidth
maximum sampling rate
total power dissipation
at Vi(dif)(FS)
at Vi(dif)(max)
with DPGAEN LOW
with DPGAEN HIGH
MIN.
3.15
3.0
2.7
TYP.
3.3
3.3
3.3
106
tbf
30
3
MAX.
3.45
3.6
3.6
UNIT
V
V
V
mA
mA
mA
mA
− ±3.0 tbf LSB
− ±1.0 tbf LSB
− ±0.5 tbf LSB
− ±0.5 tbf LSB
tbf 2 mVrms
120 MHz
30 tbf
MHz
100 − − Msps
460 500 mW
tbf tbf mW
1999 Sep 16
2





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