TDA8960

INTEGRATED CIRCUITS DATA SHEET TDA8960 ATSC 8-VSB demodulator and decoder Preliminary specification File under Integrated Circuits, IC02 1999 Jun 14 Philips Semiconductors Preliminary specification ATSC 8-VSB demodulator and decoder FEATURES General features One-chip Advanced Television Systems Committee (ATSC)-compliant demodulator and concatenated trellis (Viterbi)/Reed Solomon decoder with de-interleaver and de-randomizer 0.4 µm process 3.3 V device 64-lead QFP64 package Boundary scan test Output format: 8-bit wide bus. DOCUMENT REFERENCES 8-VSB demodulator On-chip digital circuitry for tuner Automatic Gain Control (AGC) Square root raised cosine filter with 11.5% roll-off factor Fully internal carrier recovery loop Mostly internal clock recovery and AGC loops with programmable loop filters External indication of demodulator lock. Adaptive equalizer Feed forward including a Decision Feedback Equalizer (DFE) structure Range of −2.3 to +10.5 µs Adaptation based on ATSC field sync (trained) and/or 8-VSB data (blind) Trellis (Viterbi) decoder Rate 2⁄3 (Rate 1⁄2 Ungerboeck code based). Reed Solomon decoder (207, 187 and T = 10) Reed Solomon code Internal convolutional de-interleaving (I = 52; using internal memory) External indication of uncorrectable error; transport error indicator bit in Motion Picture Export Group (MPEG) packet header is also set Followed by de-randomizer based on ATSC standard. ORDERING INFORMATION TYPE NUMBER TDA...