TDA9852

INTEGRATED CIRCUITS DATA SHEET TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor Preliminary specification Supersedes data of 1996 Feb 28 File under Integrated Circuits, IC02 1997 Mar 11 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor FEATURES Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus High integration level with automatically tuned integrated filters Input level adjustment I2C-bus controlled Alignment-free SAP processing dbx noise reduction circuit Power supply I2C-bus transceiver. Stereo decoder Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I2C-bus. Audio processor Selector for internal and external signals (line in) Automatic volume level control (control range +6 to −15 dB) Interface for external noise reduction circuits Volume control (control range +16 to −71 dB) Special loudness characteristic automatically controlled in combination with volume setting (control range 28 dB) Audio signal zero crossing detection between any volume step switching Mute control at audio signal zero crossing Mute control via I2C-bus. ORDERING INFORMATION TYPE NUMBER TDA9852 TDA9852H PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION TDA9852 The TDA9852 is a bipolar-integrated BTSC stereo decoder with hi-fi audio processor (I2C-...