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Part Number TDOV
Manufacturers Xilinx Inc
Logo Xilinx  Inc
Description XC1800 Series of In-System Programmable Configuration PROMs
Datasheet TDOV DatasheetTDOV Datasheet (PDF)

d 0 ® XC1800 Series of In-System Programmable Configuration PROMs 0 6* September 17, 1999 (Version 1.3) Preliminary Product Specification Features • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range IEEE Std 1149.1 boundary-scan (JTAG) support Simple interface to the FPGA; could be configured to use only one user I/O pin Cascadable for storing longer or multiple b.

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d 0 ® XC1800 Series of In-System Programmable Configuration PROMs 0 6* September 17, 1999 (Version 1.3) Preliminary Product Specification Features • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range IEEE Std 1149.1 boundary-scan (JTAG) support Simple interface to the FPGA; could be configured to use only one user I/O pin Cascadable for storing longer or multiple bitstreams Dual configuration modes - Serial Slow/Fast configuration (up to 15 mHz). - Parallel Low-power advanced CMOS FLASH process 5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals. 3.3 V or 2.5 V output capability Available in PC20, SO20, PC44 and VQ44 packages. Design support using the Xilinx Alliance and Foundation series software packages. JTAG command initiation of standard FPGA configuration. Description Xilinx introduces the XC1800 series of in-system programmable configuration PROMs. Initial devices in this 3.3V family are a 4 megabit, a 2 megabit, a 1 megabit, a 512 Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA or CPLD configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROM’s DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 5 Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC1700L one-time programmable Serial PROM family. CLK CE OE/Reset • • • • • • • • • • TCK TMS TDI TDO Control and JTAG Interface Data Memory Address Data Serial or Parallel Interface CEO D0 DATA (Serial or Parallel (Express/SelectMAP) Mode) D1 - D7 Express Mode and SelectMAP Interface CF 99020300 Figure 1: XC1800 Series Block Diagram September 17, 1999 (Version 1.3) 1 R XC1800 Series of In-System Programmable Configuration PROMs Pinout and Pin Description Table 1: Pin Names and Descriptions Pin Name D0 Boundary Scan Order 4 3 D1 6 5 D2 2 1 D3 8 7 D4 24 23 D5 10 9 D6 17 16 D7 14 13 CLK 0 Function Pin Description 44-pin VQFP 40 44-pin PLCC 2 20-pin SOIC & PLCC 1 DATA OUT D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. OUTPUT ENABLE DATA OUT D0- D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in OUTPUT express mode. ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is low and OE/RESET is high. 29 35 16 42 4 2 27 33 15 9 15 7* 25 31 14 14 20 9 19 25 12 43 5 3 20 OE/ RESET 19 18 CE 15 When Low, this input holds the address counter reset and the DATA output at DATA OUT high impedance. OUTPUT ENABLE DATA IN When CE is High, this pin puts the device into standby mode. The DATA output pin is at High impedance, and the device is in low power standby mode. DATA IN 13 19 8 15 21 10 CF 22 21 DATA OUT Allows JTAG CONFIG instruction to initiate FPGA configuration without powerDATA IN ing down FPGA. 10 16 7* 2 September 17, 1999 (Version 1.3) R XC1800 Series of In-System Programmable Configuration PROMs Pin Name CEO Boundary Scan Order 13 14 44-pin VQFP 21 44-pin PLCC 27 20-pin SOIC & PLCC 13 Function Pin Description DATA OUT Chip Enable (CEO) output is connected to the CE input of the next PROM in the OUTPUT chain. This output is Low when the CE ENABLE and OE/RESET inputs are active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When the PROM has been read, CEO will follow CE as long as OE/ RESET is High. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. CEO can be programmed to be either active High or active Low. GND is the ground connection. MODE SELECT The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal.


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