Voltage Switch. TEA1024 Datasheet

TEA1024 Switch. Datasheet pdf. Equivalent


Part TEA1024
Description Zero Voltage Switch
Feature TEA1024/ TEA1124 Zero Voltage Switch with Fixed Ramp Description The monolithic integrated bipolar c.
Manufacture TEMIC Semiconductors
Datasheet
Download TEA1024 Datasheet

TEA1024/ TEA1124 Zero Voltage Switch with Fixed Ramp Descrip TEA1024 Datasheet
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TEA1024
TEA1024/ TEA1124
Zero Voltage Switch with Fixed Ramp
Description
The monolithic integrated bipolar circuit, TEA1024/
TEA1124 is a zero voltage switch for triac control in
domestic equipments. It offers not only the control of a
triac in zero crossing mode but also the possibility of
power control. This is why the IC contains a mains
synchronized ramp generator with 640 ms (1280 ms)
duration (50 Hz). It is suitable for a typical load of 750 W
(1000 W) meeting the Flicker Standard. (values in
brackets relate to TEA1124.)
Features
D Direct supply from the mains
D Definite IC switching characteristics
D Very few external components
D Full wave drive – no dc component in the load circuit
D Current consumption 1.5 mA
D Output short circuit protected
D Simple power control
D Integrated ramp generator
D Reference voltage variable by external resistance
D Pulse position optimization
Package: DIP8
Block Diagram
95 10871
390 kW
R2
(Rsync)
D1 1N4007
WR1 22 k /
2W
Load
1000 W
L
7
1
56 kW
Ramp generator
TEA 1024 – 640 ms
TEA 1124 – 1280 ms
Sync. logic
min.
100 kW
max.
Protection
2
43 kW
Comparator
+
3
8
NC NC
4
Supply
C1
6
100 mF
16 V
VM=
230 V ~
TIC
236N MT2
5
Pulse
amplifier
RG
68 W
MT1
N
Figure 1. Typical block diagram – open loop power control
TELEFUNKEN Semiconductors
Rev. A1, 24-May-96
1 (8)



TEA1024
TEA1024/ TEA1124
Power Supply and its Limitations
Full-Wave Logic
The voltage limitation contained in the IC allows it to be
ăpowered from mains via series resistance R1 and recti–
fying diode D1 between Pin 6 (+ Pol/ ) and Pin 4 (–VS).
The capacitor C1 smooths the supply voltage
(see figure 1).
An internal temperature-compensated limiting circuit
protects the module from random peaks of voltage on the
mains, and delivers a defined reference voltage during the
negative half-cycle.
Synchronization
The full-wave logic ensures that only pairs of pulses can
be released, and that these always begin with the positive
dv/dt. The load is thus switched on for a minimum of one
complete mains cycle. This means that the triac receives
a minimum of two driving pulses, so that the unwanted
d.c. component in the load circuit is definitely eliminated.
Pulse Amplifier
The pulse amplifier connected to the output of the full-
wave logic circuit, is proof against continuos
short-circuits, and delivers negative output pulses of typ.
75 mA, via an integrated limiting resistance, to Pin 5.
Ramp Generator (Figures 3, 4)
Figure 2. Pulse position optimization
The logic function is synchronized by means of a separate
resistance R2 connected between Pin 7 and phase
(voltage-synchronization). The width of the pulse can be
varied between wide limits by choice of Rsync. The larger
the value chosen, the wider the output pulse is on Pin 5.
Automatic optimization of the phase of the pulse is
necessary, since the latching current of the triac exceeds
the steady current by a factor of 3.
Ramp voltage which is generated in the IC is available not
only at reference Pin 1, but also at the non-inverted input
of the comparator.
The current sink which is controlled by D/A converter
influences the internal reference voltage at Pin 1 specified
by voltage divider. The current sink is turned-off in the
reset state of the D/A converter so that the voltage at Pin 1
is primarily specified via the internal voltage divider
(ramp starting voltage).
In the maximum state of the 4 stage (5 stage – TEA1124)
D/A converter, the current sink overtakes the maximum
current, whereby the ramp’s final (end) voltage has
reached. External resistance Rx, Ry shown in figure 4 are
in position to influence the initial ramp voltage as well as
the ramp amplitude. If the external resistances ratio Rx,
Ry is the same as that of the internal ratio, the ramp
voltage at the beginning remains maintained (constant),
only the amplitude is compressed.
V1
–1.3 V
t
2.2 V
The phase of the pulse is chosen so that ca. 1/3 of the pulse –3.8 V
width appears before the transition through null and 2/3
T= 640 ms
after it (see electrical characteristics and figure 2).
(T= 1280 ms)
16 stage ramp
In order to avoid phase-clipping after the switch-on the 95 11410
first third of the first pulse is automatically suppressed.
Figure 3. Ramp diagram without external circuit
2 (8) TELEFUNKEN Semiconductors
Rev. A1, 24-May-96





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