SCANNING PROCESSOR. TEA2130 Datasheet

TEA2130 PROCESSOR. Datasheet pdf. Equivalent

Part TEA2130
Description TV AND SATELLITE DECODER SCANNING PROCESSOR
Feature TEA2130 TV AND SATELLITE DECODER SCANNING PROCESSOR . . . . . . . . . . . AUTOMATIC TIME CONSTANT .
Manufacture ST Microelectronics
Datasheet
Download TEA2130 Datasheet

TEA2130 TV AND SATELLITE DECODER SCANNING PROCESSOR . . . . TEA2130 Datasheet
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TEA2130
TEA2130
TV AND SATELLITE DECODER SCANNING PROCESSOR
. AUTOMATIC TIME CONSTANT SWITCHING
FOR VCR
. DIGITAL VIDEO IDENTIFICATION CIRCUIT
. 500kHz RESONATOR OSCILLATOR
. NO LINE AND FRAME OSCILLATOR AD-
JUSTMENT
. DUAL PLL FOR LINE DEFLECTION
. SUPER SANDCASTLE OUTPUT
. AUTOMATIC 50Hz/60Hz STANDARD IDENTI-
FICATION
. EXCELLENT INTERLACING CONTROL
. FRAME SAFETY INPUT
. FRAME SAWTOOTH GENERATOR
. FULLY ESD AND LATCH-UP PROTECTED
DIP20
(Plastic Package)
DESCRIPTION
The TEA2130 is a complete (horizontal and verti-
cal) deflection processor, for TV applications and
all applications which require a flexible, high per-
formance scanning processor (Satellite Decoder,
Video Multimedia).
ORDER CODE : TEA2130
PIN CONNECTIONS
REFERENCE VOLTAGE
VCR DETECTOR OUTPUT
Φ1 FILTER
GROUND
V CC
FRAME SAFETY INPUT
IDENTIFICATION OUTPUT
LINE SAW-TOOTH
CURRENT REFERENCE
LINE MONOSTABLE CAPACITOR
1
2
3
4
5
6
7
8
9
10
20 NOISE MEASUREMENT OUTPUT
19 VIDEO INPUT
18 50% CAPACITOR
17 VCO INPUT
16 FRAME SAW-TOOTH GENERATOR
15 FRAME SAW-TOOTH OUTPUT
14 Φ2 FILTER
13 LINE FLYBACK INPUT
12 SUPER SANDCASTLE OUTPUT
11 LINE OUTPUT
September 1993
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TEA2130
TEA2130
BLOCK DIAGRAM
18
17
16 15
19
LINE SYNCHRO
VCO
FRAME
SEPARATOR
500kHz
SEPARATOR
LS
2µs
20 NOISE
MEASURMENT
1 VCC /2
Mute
VREF
Φ1 500kHz
2 AUTO VCR
SWITCH
FRAME
LOGIC
3
Burst
ϕ1
ϕ2 Mute
DIGITAL MUT
2µs
Mute
LINE LOGIC
50/60Hz
Ident 60Hz
FRAME SAWTOOTH
GENERATOR
RAZ
Φ2
14
Burst
SUPER SAND
CASTLE GENERATOR
Inhibition
13
12
PHASE CONTROL
LINE OUTPUT
LINE
MONOST
LINE
OUTPUT
11
1.3V
Mute
VOLTAGE
REFERENCE
10
1.3V
9
FRAME SECURITY
DETECTION
50/60Hz &
MUT OUTPUT
RAZ LINE SAWTOOTH
GENERATOR
8
4
GND
5
VC C
6
7
GENERAL DESCRIPTION
Introduction
This integrated circuit uses high density I2L bipolar
technology and combines analog signal process-
ing with digital processing.
Timing signals are obtained from a voltage-control-
led oscillator (VCO) operating at 500kHz by means
of a cheap ceramic resonator. This avoid the fre-
quency adjustment normally required with line and
frame oscillators.
A chain of dividers and appropriate logic circuitry
produces very accurate defined sampling pulses
and the necessary timing signals.
Internal Functions
- Horizontal scanning processor
- Frame scanning processor
- B class frame output stage using an external
power amplifier with flyback generator
- Line and frame synchronization separation
- Dual phase-locked loop horizontal scanning
- High performance frame and line synchronization
with interlacing control.
- Supersandcastle generator with reduced burst
gate pulse for 60Hz
- Automatic 50Hz / 60Hz standard identification
- Frame saw-tooth generator
- Digital video identification circuit
- Very steady free running mode of the line and
frame oscillator when no video is detected. This
allows on screen display without phase Jitter in
research mode of the tuner
- Automatic VCR mode recognition for time con-
stant switching
- Frame safety input
WORKING DESCRIPTION
Synchronization Separator
Line synchronization separator is clamped to black
level of input video signal with synchronization
pulse bottom level measurement.
The synchronization pulses are divided centrally
between the black level and the synchronization
pulse bottom level, to improve performance on
video signal in noise conditions.
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