T1/E1 Framer. TFRA08C13 Datasheet

TFRA08C13 Framer. Datasheet pdf. Equivalent

TFRA08C13 Datasheet
Recommendation TFRA08C13 Datasheet
Part TFRA08C13
Description TFRA08C13 OCTAL T1/E1 Framer
Feature TFRA08C13; Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Features s Facility Data Link Fea.
Manufacture Agere Systems
Datasheet
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Agere Systems TFRA08C13
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Features
s Eight independent T1/E1 transmit and receive
framers.
s Internal DS1 transmit clock synthesis—no external
oscillator necessary.
s Comprehensive alarm reporting and performance
monitoring:
— Programmable automatic and on-demand alarm
transmission.
s Automatic facility data link:
— Automatic transmission of ESF performance
report message.
s Common 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s TDM highway.
s Dual- or single-rail line-side I/O.
s Supports one second polling interval for perfor-
mance monitoring.
s IEEE * Std. 1149.1 JTAG boundary scan.
s 3.3 V low-power CMOS with 5 V tolerant inputs.
s Available in 352-pin PBGA.
T1/E1 Framer Features
s Supports T1 framing modes ESF, D4, SLC ®-96,
T1DM DDS.
s Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.
s Supports unframed transmission format.
s T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;
SLC-96 2-state, 4-state, 9-state, and 16-state. E1
signaling modes: transparent and CAS.
s Alarm reporting and performance monitoring per
AT&T, ANSI , and ITU-T standards.
s Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.
Facility Data Link Features
s HDLC or transparent mode.
s Automatic transmission of the ESF performance
report messages (PRM).
s Detection of the ESF PRM.
s Detection of the ANSI ESF FDL bit-oriented codes.
s 64-byte FIFO in both transmit and receive direc-
tions.
s Programmable FIFO full and empty level interrupt.
s User-programmable microprocessor interface.
Microprocessor Interface
s 33 MHz read and write access.
s 12-bit address, 8-bit data interface.
s Intel or Motorola§ style control interfaces.
s Directly addressable internal registers.
s Programmable interrupts.
Applications
s DS3 and E3 port cards for narrowband DXCs.
s Multiservice switches.
s High density DS1 and E1 port cards.
s Frame relay access devices.
s Byte-synchronous SDH/SONET mapping.
s SONET and SDH drop alignment.
s IP and packet routers.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
ANSI is a registered trademark of American National Standards
Institute, Inc.
Intel is a registered trademark of Intel Corporation.
§ Motorola is a registered trademark of Motorola, Inc.



Agere Systems TFRA08C13
TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
T1/E1 Framer Features ......................................................................................................................................... 1
Facility Data Link Features ....................................................................................................................................... 1
Microprocessor Interface .......................................................................................................................................... 1
Applications .............................................................................................................................................................. 1
Feature Descriptions .............................................................................................................................................. 10
T1/E1 Framer Feature Descriptions .................................................................................................................... 10
Functional Description ............................................................................................................................................ 11
Pin Information ....................................................................................................................................................... 15
LIU-Framer Interface .............................................................................................................................................. 29
LIU-Framer Physical Interface............................................................................................................................. 29
Line Encoding...................................................................................................................................................... 31
DS1: Zero Code Suppression (ZCS)................................................................................................................... 31
CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 33
Frame Formats ....................................................................................................................................................... 34
T1 Framing Structures......................................................................................................................................... 34
T1 Loss of Frame Alignment (LFA) ..................................................................................................................... 41
T1 Frame Recovery Alignment Algorithms.......................................................................................................... 42
T1 Robbed-Bit Signaling ..................................................................................................................................... 43
CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ................... 45
CEPT 2.048 Basic Frame Structure .................................................................................................................... 46
CEPT Loss of Basic Frame Alignment (LFA) ...................................................................................................... 48
CEPT Loss of Frame Alignment Recovery Algorithm ......................................................................................... 48
CEPT Time Slot 0 CRC-4 Multiframe Structure .................................................................................................. 49
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA).................................................................................... 50
CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms ..................................................................... 51
CEPT Time Slot 16 Multiframe Structure ............................................................................................................ 55
CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)......................................................................... 56
CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm.............................................................. 56
CEPT Time Slot 0 FAS/NOT FAS Control Bits....................................................................................................... 56
FAS/NOT FAS Si- and E-Bit Source ................................................................................................................... 56
NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ..................................................................................... 57
NOT FAS Sa-Bit Sources.................................................................................................................................... 57
Sa Facility Data Link Access ............................................................................................................................... 58
NOT FAS Sa Stack Source and Destination ....................................................................................................... 59
CEPT Time Slot 16 X0—X2 Control Bits............................................................................................................. 61
Signaling Access .................................................................................................................................................... 61
Transparent Signaling ......................................................................................................................................... 61
DS1: Robbed-Bit Signaling.................................................................................................................................. 61
CEPT: Time Slot 16 Signaling............................................................................................................................. 62
Auxiliary Framer I/O Timing ................................................................................................................................... 63
Alarms and Performance Monitoring ...................................................................................................................... 67
Interrupt Generation ............................................................................................................................................ 67
Alarm Definition ................................................................................................................................................... 67
Event Counters Definition ................................................................................................................................... 73
Loopback and Transmission Modes.................................................................................................................... 75
Line Test Patterns ............................................................................................................................................... 78
Receive Line Pattern Monitor—Using Register FRM_SR7 ................................................................................. 80
Automatic and On-Demand Commands ............................................................................................................. 82
Facility Data Link .................................................................................................................................................... 84
2 Lucent Technologies Inc.



Agere Systems TFRA08C13
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Table of Contents (continued)
Contents
Page
Receive Facility Data Link Interface.....................................................................................................................84
Transmit Facility Data Link Interface....................................................................................................................90
HDLC Operation ..................................................................................................................................................91
Transparent Mode................................................................................................................................................93
Diagnostic Modes ................................................................................................................................................95
Phase-Lock Loop Circuit .........................................................................................................................................96
Framer-System Interface ........................................................................................................................................98
DS1 Modes ..........................................................................................................................................................98
CEPT Modes........................................................................................................................................................98
Receive Elastic Store...........................................................................................................................................98
Transmit Elastic Store..........................................................................................................................................98
Concentration Highway Interface ............................................................................................................................98
CHI Parameters ...................................................................................................................................................99
CHI Frame Timing..............................................................................................................................................101
CHI Offset Programming....................................................................................................................................104
JTAG Boundary-Scan Specification ..................................................................................................................... 105
Principle of the Boundary Scan..........................................................................................................................105
Test Access Port Controller ...............................................................................................................................107
Instruction Register ............................................................................................................................................109
Boundary-Scan Register....................................................................................................................................110
BYPASS Register ..............................................................................................................................................110
DCODE Register................................................................................................................................................110
3-State Procedures ............................................................................................................................................110
Microprocessor Interface.......................................................................................................................................111
Overview ............................................................................................................................................................111
Microprocessor Configuration Modes ................................................................................................................111
Microprocessor Interface Pinout Definitions ......................................................................................................112
Microprocessor Clock (MPCLK) Specifications .................................................................................................112
Microprocessor Interface Register Address Map ...............................................................................................113
I/O Timing ..........................................................................................................................................................113
Reset.................................................................................................................................................................... 118
Hardware Reset (Pin C19).................................................................................................................................118
Software Reset/Software Restart.......................................................................................................................118
Interrupt Generation ..............................................................................................................................................118
Register Architecture.............................................................................................................................................119
Global Register Architecture .................................................................................................................................123
Global Register Structure......................................................................................................................................123
Framer Block Interrupt Status Register (GREG0)..............................................................................................123
Framer Block Interrupt Enable Register (GREG1).............................................................................................124
FDL Block Interrupt Status Enable Register (GREG2) ......................................................................................124
FDL Block Interrupt Enable Register (GREG3) .................................................................................................124
Global Control Register (GREG4)......................................................................................................................125
Device ID and Version Registers (GREG5—GREG7) .......................................................................................125
Global Control Register (GREG8)......................................................................................................................126
Global PLLCK Control Register (GREG9) .........................................................................................................127
Framer Register Architecture ................................................................................................................................127
Framer Status/Counter Registers ......................................................................................................................128
Framer Parameter/Control Registers .................................................................................................................141
FDL Register Architecture.....................................................................................................................................168
FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);
(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)) .................................................................169
Lucent Technologies Inc.
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