bus buffer. P82B96 Datasheet

P82B96 buffer. Datasheet pdf. Equivalent

Part P82B96
Description Dual bi-directional bus buffer
Feature INTEGRATED CIRCUITS P82B96 Dual bi-directional bus buffer Product data Supersedes data of 2003 Apr .
Manufacture NXP
Datasheet
Download P82B96 Datasheet



P82B96
INTEGRATED CIRCUITS
P82B96
Dual bi-directional bus buffer
Product data
Supersedes data of 2003 Apr 02
2004 Mar 26
Philips
Semiconductors



P82B96
Philips Semiconductors
Dual bi-directional bus buffer
Product data
P82B96
PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP
Sx 1
8 VCC
Rx 2
7 Sy
FEATURES
Bi-directional data transfer of I2C-bus signals
Isolates capacitance allowing 400 pF on Sx/Sy side and
4000 pF on Tx/Ty side
Tx/Ty outputs have 60 mA sink capability for driving
low impedance or high capacitive buses
400 kHz operation over at least 20 meters of wire (see AN10148)
Supply voltage range of 2 V to 15 V with I2C logic levels on Sx/Sy
side independent of supply voltage
Splits I2C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals
for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.
Low power supply current
ESD protection exceeds 3500 V HBM per JESD22-A114,
250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101
Latch-up free (bipolar process with no latching structures)
Packages offered: DIP, SO, and TSSOP
TYPICAL APPLICATIONS
Interface between I2C buses operating at different logic levels
(e.g., 5 V and 3 V or 15 V)
Interface between I2C and SMB (350 µA) bus standard.
Simple conversion of I2C SDA or SCL signals to multi-drop
differential bus hardware, e.g., via compatible PCA82C250.
Interfaces with Opto-couplers to provide Opto isolation between
I2C-bus nodes up to 400 kHz.
DESCRIPTION
The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I2C-bus and a
range of other bus configurations. It can interface I2C-bus logic
signals to similar buses having different voltage and current levels.
For example it can interface to the 350 µA SMB bus, to 3.3 V logic
devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I2C
protocols or clock speed. The IC adds minimal loading to the I2C
node, and loadings of the new bus or remote I2C nodes are not
transmitted or transformed to the local node. Restrictions on the
number of I2C devices in a system, or the physical separation
between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
alternative bi-directional signal line with I2C properties.
Tx 3
GND 4
6 Ry
5 Ty
SU01011
PINNING
SYMBOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁSx
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁRx
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTx
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁGND
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTy
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁRy
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁSy
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVCC
PIN DESCRIPTION
1 I2C-bus (SDA or SCL)
2 Receive signal
3 Transmit signal
4 Negative Supply
5 Transmit signal
6 Receive signal
7 I2C-bus (SDA or SCL)
8 Positive supply
SPECIAL NOTE:
Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I2C signals
do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
buffer. A “regular I2C low” applied at the Rx/Ry of a P82B96 will be
propagated to Sx/Sy as a “buffered low” with a slightly higher
voltage level. If this special “buffered low” is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
“regular I2C-bus low” and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
for, and compatible with, the normal I2C logic voltage levels of I2C
master and slave chips—or even Tx/Rx signals of a second P82B96
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C logic
voltage levels of all I2C parts. There are NO restrictions on the
interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see Application
Note AN255.
2004 Mar 26
2





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)