sync proc.. P83C380 Datasheet

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P83C380 Datasheet
Recommendation P83C380 Datasheet
Part P83C380
Description Microcontrollers for monitors with DDC interface/ auto-sync detection and sync proc.
Feature P83C380; INTEGRATED CIRCUITS DATA SHEET P83Cx80; P87C380 Microcontrollers for monitors with DDC interface, .
Manufacture NXP
Datasheet
Download P83C380 Datasheet




NXP P83C380
INTEGRATED CIRCUITS
DATA SHEET
P83Cx80; P87C380
Microcontrollers for monitors
with DDC interface, auto-sync
detection and sync proc.
Product specification
File under Integrated Circuits, IC20
1997 Dec 12



NXP P83C380
Philips Semiconductors
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
Product specification
P83Cx80; P87C380
CONTENTS
1
1.1
1.2
2
3
4
5
5.1
5.2
6
6.1
7
7.1
7.2
7.3
8
8.1
8.2
8.3
8.4
9
10
10.1
10.2
11
11.1
11.2
11.3
11.4
12
13
13.1
13.2
13.3
14
14.1
14.2
14.3
15
15.1
FEATURES
Differences from the 80C51 core
Memory
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pin description
FUNCTIONAL DESCRIPTION
General
MEMORY ORGANIZATION
Program memory
Internal data memory
Additional Special Function Registers
INTERRUPTS
Priority level structure
How interrupts are handled
Interrupt Enable Register (IE)
Interrupt Priority Register (IP)
WATCHDOG TIMER
INPUT/OUTPUT (I/O)
The alternative functions for Port 0, Port 1,
Port 2 and Port 3
EMI (Electromagnetic Interference) reduction
REDUCED POWER MODES
Power Control Register
Idle mode
Power-down mode
Status of external pins
OSCILLATOR
RESET
External reset
Power-on-reset
T2 (Watchdog Timer) overflow
ANALOG CONTROL (DC)
8-bit PWM outputs (PWM0 to PWM9)
14-bit PWM output (PWM10)
A typical PWM output application
ANALOG-TO-DIGITAL CONVERTER (ADC)
Conversion algorithm
16
16.1
17
17.1
17.2
17.3
17.4
17.5
17.6
18
19
19.1
19.2
19.3
20
21
22
23
24
25
26
27
28
29
29.1
29.2
29.3
30
31
32
DIGITAL-TO-ANALOG CONVERTER (DAC)
8-bit Data Registers for the DAC outputs
(DACn; n = 0 to 3)
DISPLAY DATA CHANNEL (DDC)
INTERFACE
Special Function Registers related to the DDC
interface
Host type detection
DDC1 protocol
DDC2B protocol
DDC2AB/DDC2B+ protocol
RAM buffer for the system and DDC application
I2C-BUS INTERFACE
HARDWARE MODE DETECTION
Special Function Register for mode detection
and sync separation
System description
System operation
POWER MANAGEMENT
CONTROL MODES
ONE TIME PROGRAMMABLE (OTP)
VERSION
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
DIGITAL-TO-ANALOG CONVERTER
CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINE
SOLDERING
Introduction
Soldering by dipping or by wave
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1997 Dec 12
2



NXP P83C380
Philips Semiconductors
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
Product specification
P83Cx80; P87C380
1 FEATURES
80C51 type core
On-chip oscillator with a maximum frequency of 16 MHz
(maximum 0.75 µs instruction cycle)
A DDC interface:
– That fully supports DDC1 with specific hardware
– That is DDC2B, DDC2B+, DDC2AB (ACCESS.bus)
compliant, based on a dedicated hardware I2C-bus
interface.
– Contains a specific AUX-RAM buffer with
programmable size (128 or 256 bytes) that can be
used for DDC operation and shared as system RAM
Automatic mode detection by hardware to capture the
following information:
– HSYNC frequency with 12-bit resolution
– VSYNC frequency with 12-bit resolution
– HSYNC and VSYNC polarity
– HSYNC and VSYNC presence; needed for the VESA
Device Power Management Signalling (DPMS)
standard
On-chip sync processor comprising:
– Composite sync separation
– Free running mode
– Clamping
– Pattern generation
Two specific ports for the software I2C-bus interface
4 analog voltage outputs derived from an 8-bit
Digital-to-Analog Converter (DAC)
Ten 8-bit Pulse Width Modulation (PWM) outputs for
digital control application
One 14-bit PWM output for digital control application
One 4-bit Analog-to-Digital Converter (ADC) with 2 input
channels (for keyboard interface)
LED driver port (Port 0); eight port lines with 10 mA drive
capability
One 8-bit port only for I/O function
20 derivative I/O ports with the specific port type
configuration in each alternative function
Watchdog Timer with a programmable interval
On-chip Power-on-reset for low power detection
Special Idle and Power-down modes for reduced power
operation
Optimized for Electromagnetic Compatibility (EMC)
Operating temperature: 25 to +85 °C
Single power supply: 4.4 to 5.5 V.
1.1 Differences from the 80C51 core
No external memory connection; signals EA, ALE and
PSEN are not present.
Port 1, Port 2 and Port 3 (P3.0 to P3.3 only) mixed with
other derivative functions.
Timer 0/Counter 0 and Timer 1/Counter 1: external
input is removed.
External interrupt 0/INT0 replaced by Mode detection
function.
Standard serial interface (UART) and its control register
are removed.
Wake-up from Power-down mode is also possible by
means of an interrupt.
1.2 Memory
Table 1 ROM/RAM sizes
DEVICE
P83C880
P83C180
P83C280
P83C380
P87C380 (OTP)
MEMORY
ROM
RAM
8 kbytes
16 kbytes
24 kbytes
32 kbytes
16 kbytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
1997 Dec 12
3







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