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MULTI-CHIP PACKAGE. TH50VSF3680 Datasheet |
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TH50VSF3680/3681AASB
TENTATIVE TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
DESCRIPTION
The TH50VSF3680/3681AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a
67,108,864-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration.
The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write
or Erase operation. The TH50VSF3680/3681AASB can range from 2.7 V to 3.3 V. The TH50VSF3680/3681AASB is
available in a 69-pin BGA package, making it suitable for a variety of design applications.
FEATURES
• Power supply voltage
VCCs = 2.7 V~3.3 V
VCCf = 2.7 V~3.3 V
• Data retention supply voltage
VCCs = 1.5 V~3.3 V
• Current consumption
Operating: 45 mA maximum (CMOS level)
Standby: 10 µA maximum (SRAM CMOS level)
Standby: 10 µA maximum (FLASH)
• Block erase architecture for flash memory
8 × 8 Kbytes
63 × 64 Kbytes
• Organization
CIOF CIOS
Flash Memory
SRAM
VCC
VCC
VSS
VCC
VSS
VSS
4,194,304 words of 16 bits
4,194,304 words of 16 bits
8,388,608 words of 8 bits
524,288 words of 16 bits
1,048,576 words of 8 bits
1,048,576 words of 8 bits
• Function mode control for flash memory
Compatible with JEDEC-standard commands
• Flash memory functions
Simultaneous Read/Write operations
Auto-Program
Auto Chip Erase, Auto Block Erase
Auto Multiple-Block Erase
Program Suspend/Resume
Block-Erase Suspend/Resume
Data Polling/Toggle Bit function
Block Protection/Boot Block Protection
Automatic Sleep, Hidden ROM Area Supports
Common Flash Memory Interface (CFI)
Byte/Word Mode
• Erase and Program cycle for flash memory
105 cycles (typical)
• Boot block architecture for flash memory
TH50VSF3680AASB: Top boot block
TH50VSF3681AASB: Bottom boot block
• Package
P-FBGA69-1209-0.80A3: 0.31 g (typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
• Case: CIOF = VCC, CIOS = VCC (×16, ×16)
1 2 3 4 5 6 7 8 9 10
A NC
NC
B NC
NC
C NC
A7 LB WP/ACC WE A8 A11
D A3 A6 UB RESET CE2S A19 A12 A15
E A2 A5 A18 RY/BY A20 A9 A13 A21
F NC A1 A4 A17
A10 A14 NC NC
G NC A0 VSS DQ1
H CEF OE DQ9
DQ3
DQ6 DU A16
DQ4 DQ13 DQ15 CIOF
NC
J CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS
K DQ8 DQ2 DQ11 CIOS DQ5 DQ14
L NC
NC
M NC
NC
A0~A22 Address Inputs
A12S
A12 Input for SRAM
A12F
A12 Input for Flash Memory
SA A19 Input for SRAM
DQ0~DQ15 Data Inputs/Outputs
CE1S , CE2S Chip Enable Inputs for SRAM
CEF
Chip Enable Input for Flash Memory
OE Output Enable Input
WE Write Enable Input
LB , UB Data Byte Control Input
RY/BY
Ready/Busy Output
RESET Hardware Reset Input
WP/ACC Write Protect/Program Acceleration Input
CIOS
Word Enable Input for SRAM
CIOF
Word Enable Input for Flash Memory
VCCs
VCCf
VSS
NC
Power Supply for SRAM
Power Supply for Flash Memory
Ground
Not Connected
DU Don’t Use
000707EBA2
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2001-03-06 1/55
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PIN ASSIGNMENT (TOP VIEW)
• Case: CIOF = VCC, CIOS = VSS (×16, ×8)
1 2 3 4 5 6 7 8 9 10
A NC
NC
B NC
NC
C NC
A7 DU WP/ACC WE A8 A11
D A3 A6 DU RESET CE2S A19 A12 A15
E A2 A5 A18 RY/BY A20 A9 A13 A21
F NC A1 A4 A17
A10 A14 NC NC
G NC A0 VSS DQ1
H CEF OE DQ9
DQ3
DQ6 SA A16
DQ4 DQ13 DQ15 CIOF
NC
J CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS
K DQ8 DQ2 DQ11 CIOS DQ5 DQ14
L NC
NC
M NC
NC
• Case: CIOF = VSS, CIOS = VSS (×8, ×8)
1 2 3 4 5 6 7 8 9 10
A NC
NC
B NC
NC
C NC
A7 DU WP/ACC WE A8 A11
D A3 A6 DU RESET CE2S A20 A13 A16
E A2 A5 A19 RY/BY A21 A9 A14 A22
F NC A1 A4 A18
A10 A15 NC NC
G NC A0 VSS DQ1
H CEF OE DU
DQ3
DQ4
DQ6 A12S A17
DU A12F CIOF
NC
J CE1S DQ0 DU VCCf VCCs DU DQ7 VSS
K DU DQ2 DU CIOS DQ5 DU
L NC
NC
M NC
NC
Note: A12F and A12S should be wired and used as A12 pin.
TH50VSF3680/3681AASB
000707EBA2
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2001-03-06 2/55
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BLOCK DIAGRAM
A0~A22
WP/ACC
RESET
CEF
TH50VSF3680/3681AASB
A0~A22
VCCf
VSS
64-Mbit
Flash Memory
DQ0~DQ15
(DQ0~DQ7)
RY/BY
CIOF
A0~A18
VCCs
VSS
DQ0~DQ15
SA
WE
OE
CE1S
CE2S
UB
LB
CIOS
8-Mbit
SRAM Memory
DQ0~DQ15
(DQ0~DQ7)
MODE SELECTION
OPERATION MODE CEF CE1S CE2S OE WE RESET UB LB WP/ACC DQ0~DQ7 DQ8~DQ15
Flash Read
L H XLH H XX
L X L LH H XX
X
X
H L HLH H LL
X
SRAM Read
H L HLH H HL
X
H L HLH H LH
X
Flash Write
L H XHL H XX
L X LHL H XX
X
X
H L HXL H L L
X
SRAM Write
H L HXL H HL
X
H L HXL H LH
X
Flash Output Disable
X H XHH X XX
X X L HH X XX
X
X
SRAM Output Disable
H X XHH X XX
H X XXX X HH
X
X
Flash Standby
H X XXX H XX
X
Flash Hardware
Reset / Standby
X X XXX L XX
X
SRAM Standby
X H XXX X XX
X X LXX X XX
X
X
Notes: L = VIL; H = VIH; X = VIH or VIL
F: Depends on flash memory operation mode. S: Depends on SRAM operation mode.
When CIOS = VCC and CIOF = VCC, Word Mode is selected for both SRAM and flash memory.
Does not apply when CEF = CE1S = VIL and CE2S = VIH at the same time.
DOUT
DOUT
DOUT
DOUT
Hi-Z
DIN
DIN
DIN
DIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
S
S
F
F
DOUT
DOUT
DOUT
Hi-Z
DOUT
DIN
DIN
DIN
Hi-Z
DIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
S
S
F
F
2001-03-06 3/55
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