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TH58100FT Datasheet, Equivalent, GATE CMOS.TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| Part | TH58100FT |
|---|---|
| Description | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| Feature | TH58100FT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1-GBIT (128M ´ 8 BITS) CMOS NAND E PR OM DESCRIPTION
The TH58100 is a single 3. 3 V 1-Gbit (1,107,296,256) bit NAND E lectrically Erasable and Programmable R ead-Only Memory (NAND E2PROM) organized as 528 bytes ´ 32 pages ´ 8192 block s. The device has a 528-byte static reg ister which allows program and read dat a to be transferred between the registe r and the memory cell array in 528-byte increments. The Erase operation is imp lemented in a single block unit (16 Kby tes + 512 bytes: 528 bytes ´ 32 pages) . The TH58100 is a . |
| Manufacture | Toshiba Semiconductor |
| Datasheet |
| Part | TH58100FT |
|---|---|
| Description | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| Feature | TH58100FT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1-GBIT (128M ´ 8 BITS) CMOS NAND E PR OM DESCRIPTION
The TH58100 is a single 3. 3 V 1-Gbit (1,107,296,256) bit NAND E lectrically Erasable and Programmable R ead-Only Memory (NAND E2PROM) organized as 528 bytes ´ 32 pages ´ 8192 block s. The device has a 528-byte static reg ister which allows program and read dat a to be transferred between the registe r and the memory cell array in 528-byte increments. The Erase operation is imp lemented in a single block unit (16 Kby tes + 512 bytes: 528 bytes ´ 32 pages) . The TH58100 is a . |
| Manufacture | Toshiba Semiconductor |
| Datasheet |
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