Low-Speed Interface. TH6503 Datasheet
USB Low-Speed Interface
The TH6503 is an integrated circuit which enables
the Universal Serial Bus (USB) to be connected to
a microcontroller. The interface module contains
all the components required to transmit data via
The TH6503 has been developed for applications
requiring a low speed interface to the USB. Any
microcontroller can be used for control purposes.
In addition to the default endpoint 0 for control
transfer up to two endpoints can be supported by
TH6503. The TH6503 has been developed in
conformity with USB Specifications 1.1.
? Complient with USB Specification 1.1
? Provides power supply for the microcontroller
? Supports up to three programmable endpoints
(3.3 volts or 5 volts)
for interrupt and control transfer in each direction ? Integrated oscillator for clock generation,
? Data transfer at USB low speed
? Supports suspend mode
? Universal serial microcontroller interface
supports 6 MHz quartz, ceramic resonator
or external clock input
? Simple external circuitry
? Register programmable
? Programmable 1.5 MHz to 6 MHz out clock for
Host / Hub
Figure 1. Typical TH6503 Sample Application
Figure 1 demonstrates a typical TH6503 applica-
tion. The TH6503 translates the data and control
signals received from the USB in a serial format
which can be read by the microcontroller. The data
is stored in a FIFO buffer and can be called up from
a standard microcontroller via a register program-
mable serial interface at any time and processed
further. Data generated by peripheries is passed
to the TH6503 with the same protocol and stored
in a FIFO buffer until it is collected by the USB. The
TH6503 translates all the data in the USB-specific
format and generates the necessary control sig-
nals. The TH6503 requires a minimum number of
external elements and can easily be implemented
in a circuitry. It provides an external clock which
can be used to activate a microcontroller.
TH6503 USB Low-Speed Interface
USB Data Transmission
The TH6503 supports the USB Specification 1.1
Data from the USB host to the device and vice
versa is transmitted serially. The data are NRZI
coded to increase transmission reliability; bit
stuffing (inserting an extra 0 bit after any
6 consecutive 1 bits) is performed and a CRC check
carried out. Bit stuffing, NRZI coding/decoding and
CRC checks or generation are performed within the
The data is transmitted in packets. Three types of
packets are defined for the USB: token, data and
The token is always passed on by the host.
It contains a PID (packet identifier) which defines the
direction of the following data transmission and the
address of the device and endpoints to be ad-
Depending on the previous token command, data is
transferred from the USB host to the TH6503 (OUT
transfer) or transferred from the TH6503 to the USB
host (IN transfer). In the process the respective
FIFOs are written (OUT) or read (IN).
The data transfer is concluded with a handshake.
If the data has been received successfully, an ACK
is sent to the data source. If no data is ready for an
IN transfer out of the TH6503, it sends an NAK
handshake instead of the data (if endpoint is ena-
Figure 2. Data Flow
The TH6503 is responsible for the data flow be-
tween the USB and the microcontroller. It ensures
that the USB transfers the data in line with the
protocol. All information in the protocol layer is
decoded by the TH6503 and carried out accord-
The data arriving from the USB host is stored in a
FIFO buffer until it is collected by the microcontroller.
Data transmitted to the USB host are imported
from a FIFO buffer which has previously been filled
by the microcontroller. A /INT signal signals to the
microcontroller that the FIFO status has been
changed by USB.
Data is transferred between the microcontroller
and the TH6503 via a software-emulating serial
interface controlled by the microcontroller.
As the TH6503 cannot interpret the content of the
data, it must be evaluated within the microcontroller.
This also applies to USB-specific control informa-
tion. All USB-typical descriptors and the associ-
ated requests must be created and managed by
The setting of the USB address serves here as an
example. After resetting the USB, the address is
set to the default value 0 (USBAddressRegister). A
specific address is transferred from the USB host
software to the device with the SET_ADDRESS
command. This command, like all SET and GET
commands, can only be decoded by the micro-
controller. The USB address is decoded in the
TH6503 with the aid of the USB AddressRegister.
For this reason the microcontroller must write the
USB address determined in this register.
The TH6503 supports the USB suspend mode.
Control takes place via the microcontroller. The
ACT bit can be used in the StatusRegister <5>
which is set on the USB for each activity. If this bit
has been inactive for a longer period of time (3 ms),
the microcontroller can set the TH6503 and itself in
the suspend mode using the SUS bit in the
BridgeConfigRegister <4>. The suspend mode
can be ended using the software or an external
signal. Apart from the suspend mode, the TH6503
also supports a number of other power saving
modes which either stop the microcontroller by
switching off the clock or set the whole USB bridge
in a power saving mode.
The TH6503 provides the clock pulse for the
microcontroller. It can be programmed with the
OCR 1 - OCR 0 bits in the BridgeConfigRegister
The TH6503 supplies 3.3V voltage to power the
microcontroller; this is produced by the adjacent
5V bus power supply connection.
TH6503 USB Low-Speed Interface
Control Signals controller
Figure 3. TH6503 Block Diagram
The data is transferred between the microcontroller and the USB bridge using the clock (SCK)
generated by the microcontroller asynchronous to the USB clock.
Data IN Transfer
(from the microcontroller to the TH6503)
Data IN transfer is initiated with rising SIN edge (IN
packet sync). Data is transferred via the SDI pin.
Initially the Adr/CntInRegister which indicates the
internal address in the TH6503 is written. Data is
subsequently transferred beginning with byte 0 to
Byte n LSB first. Bits IC3-IC0 in the Adr/CntInRegister
<3-0> contain the information on the number of
bytes to be transferred to the USB host if the target
of the data transfer was an IN FIFO.
A zero data transfer is identified with reset of IC3-
IC0 bits after writing the Adr/CntInRegister one
additional clock on SCK must be generated.
If a register is the target of the data IN transfer the
bits IC3-IC0 and TI have no meaning.
With falling SCK edge the microcontroller trans-
mit the bits to SDI and the bits are imported from
the bridge with increasing SCK edge. After each
transmission of 8 bits the respective IN FIFO value
is increased by 1. If the microcontroller writes
more data than indicated in the Adr/CntInRegister,
the oldest data are overwritten. After the final
falling edge of SCK first SDI and then SIN must be
reset to 0 to terminate the transfer. The associated
IN Done bit in the StatusRegister is reset automati-
cally to enable USB IN transfer.