CAN controller. P83C591 Datasheet

P83C591 controller. Datasheet pdf. Equivalent

P83C591 Datasheet
Recommendation P83C591 Datasheet
Part P83C591
Description Single-chip 8-bit microcontroller with CAN controller
Feature P83C591; INTEGRATED CIRCUITS DATA SHEET P8xC591 Single-chip 8-bit microcontroller with CAN controller Objec.
Manufacture NXP
Datasheet
Download P83C591 Datasheet




NXP P83C591
INTEGRATED CIRCUITS
DATA SHEET
P8xC591
Single-chip 8-bit microcontroller
with CAN controller
Objective Specification
File under Integrated Circuits, IC20
1999 Aug 19



NXP P83C591
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
CONTENTS
1 FEATURES
1.1 80C51 Related Features of the 8xC591
1.2 CAN Related Features of the 8xC591
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 FUNCTIONAL DIAGRAM
6 PINNING INFORMATION
6.1 Pinning diagram
6.2 Pin description
7 MEMORY ORGANIZATION
7.1 Program Memory
7.2 Addressing
7.3 Expanded Data RAM addressing
7.4 Dual DPTR
8 I/O FACILITIES
9 OSCILLATOR CHARACTERISTICS
10 RESET
11 LOW POWER MODES
11.1 Stop Clock Mode
11.2 Idle Mode
11.3 Power-down Mode
12 CAN, CONTROLLER AREA NETWORK
12.1 Features of the PeliCAN Controller
12.2 PeliCAN structure
12.3 Communication between PeliCAN Controller
and CPU
12.4 Register and Message Buffer description
12.5 CAN Registers
13 SERIAL I/O
14 SIO0 STANDARD SERIAL INTERFACE UART
14.1 Multiprocessor Communications
14.2 Serial Port Control Register
14.3 Baud Rate Generation
14.4 More about UART Modes
14.5 Enhanced UART
15 SIO1, I2C SERIAL IO
15.1 Modes of Operation
15.2 SIO1 Implementation and Operation
15.3 Software Examples of SIO1 Service Routines
16 TIMER 2
16.1 Features of Timer 2
17
18
18.1
18.2
18.3
19
20
20.1
20.2
20.3
20.4
20.5
21
21.1
21.2
21.3
21.4
22
22.1
23
24
25
25.1
26
26.1
26.2
27
28
28.1
29
30
WATCHDOG TIMER (T3)
PULSE WIDTH MODULATED OUTPUTS
Prescaler Frequency Control Register (PWMP)
Pulse Width Register 0 (PWM0)
Pulse Width Register 1 (PWM1)
PORT 1 OPERATION
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC features
ADC functional description
10-Bit Analog-to-Digital Conversion
10-Bit ADC Resolution and Analog Supply
Power Reduction Modes
INTERRUPTS
Interrupt Enable Registers
Interrupt Enable and Priority Registers
Interrupt priority
Interrupt Vectors
INSTRUCTION SET
Addressing Modes
LIMITING VALUES
DC CHARACTERISTICS (VALUES IN THIS
TABLE NOT CONFIRMED)
AC CHARACTERISTICS
Timing symbol definitions
EPROM CHARACTERISTICS
Program verification
Security bits
PACKAGE OUTLINES
SOLDERING
Plastic leaded-chip carriers/quad flat-packs
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1999 Aug 19
2



NXP P83C591
Philips Semiconductors
Single-chip 8-bit microcontroller with CAN controller
Objective Specification
P8xC591
1 FEATURES
1.1 80C51 Related Features of the 8xC591
Full static 80C51 Central Processing Unit available as
OTP, ROM and ROMless
16 Kbytes internal Program Memory expandable
externally to 64 Kbytes
512 bytes on-chip Data RAM expandable externally to
64 Kbytes
Three 16-bit timers/counters T0, T1 (standard 80C51)
and additional T2 (capture & compare)
10-bit ADC with 6 multiplexed analog inputs with fast
8-bit ADC option
Two 8-bit resolution, Pulse Width Modulated outputs
32 I/O port pins in the standard 80C51 pinout
I2C-bus serial I/O port with byte oriented master and
slave functions
On-chip Watchdog Timer T3
Extended temperature range: 40 to +85°C
Accelerated (prescaler 1:1) instruction cycle time
375 ns @ 16 MHz
Operation voltage range: 5 V ± 10%
Security bits:
– ROM version has 2 bits
– OTP/EPROM version has 3 bits
64 bytes Encryption array
4 level priority interrupt, 15 interrupt sources
Full-duplex enhanced UART with programmable
Baudrate Generator
Power Control Modes:
– Clock can be stopped and resumed
– Idle Mode
– Power-down Mode
ADC active in Idle Mode
Second DPTR register
ALE inhibit for EMI reduction
Programmable I/O port pins (pseudo bi-directional,
push-pull, high impedance, open drain)
Wake-up from Power-down by external interrupts
Software reset bit (AUXR1.5)
Low active reset pin
Power-on detect reset
Once mode
1.2 CAN Related Features of the 8xC591
CAN 2.0B active controller, supporting 11-bit Standard
and 29-bit Extended indentifiers
1 Mbit/s CAN bus speed with 8 MHz clock achievable
64 byte receive FIFO (can capture sequential Data
Frames from the same source as required by the
Transport Layer of higher protocols such as DeviceNet,
CANopen and OSEK)
13 byte transmit buffer
Enhanced PeliCAN core (from the SJA1000 stand-alone
CAN2.0B controller)
1.2.1 PELICAN FEATURES
Four independently configurable Screeners
(Acceptance Filters)
Each Screener has tow 32-bit specifiers:
– 32-bit Match and
– 32-bit Mask
32-bits of Mask per Screener allows unique Group
addressing per Screener
Higher layer protocols especially supported in Standard
CAN format with:
– Up to four, 11-bit ID Screeners that also Screen the
two (2) Data Bytes
– i.e., Data Frames are Screened by the CAN ID and by
Data Byte content
Up to eight, 11-bit ID Screeners half of which also
Screen the first Data Byte
All Screeners are changeable “on the fly”
Listen Only Mode, Self Test Mode
Error Code Capture, Arbitration Lost Capture, readable
Error Counters
1999 Aug 19
3







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