EDGE-TRIGGERED FLIP-FLOP. SN54LS112A Datasheet

SN54LS112A FLIP-FLOP. Datasheet pdf. Equivalent

SN54LS112A Datasheet
Recommendation SN54LS112A Datasheet
Part SN54LS112A
Description DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Feature SN54LS112A; SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop featur.
Manufacture Motorola Inc
Datasheet
Download SN54LS112A Datasheet




Motorola  Inc SN54LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
CLEAR (CD)
15(14)
J
3(11)
1(13)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
INPUTS
SD CD
LH
HL
LL
HH
HH
HH
HH
J
X
X
X
h
l
h
l
OUTPUTS
KQQ
XHL
XLH
XHH
hqq
h LH
l HL
l qq
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
Q
6(7)
SET (SD)
4(10)
K
2(12)
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4 10
3
SD
JQ
11 SD
5J
Q
9
1 CP
2 K CD Q
13 CP
12
6
K
Q
CD
7
15 14
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-185



Motorola  Inc SN54LS112A
SN54 / 74LS112A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
54
74
0.7
0.8
Input Clamp Diode Voltage
– 0.65 – 1.5
Output HIGH Voltage
54 2.5 3.5
74 2.7 3.5
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
J, K
Set, Clear
Clock
IIH
Input HIGH Current
J, K
Set, Clear
Clock
20
60
80
0.1
0.3
0.4
IIL
Input LOW Current J, K
Clear, Set, Clk
– 0.4
– 0.8
IOS
Short Circuit Current (Note 1)
– 20
– 100
ICC Power Supply Current
6.0
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay, Clock
Clear, Set to Output
30 45
15 20
15 20
V
V
V
V
V
V
µA
mA
mA
mA
mA
Unit
MHz
ns
ns
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear, Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-186



Motorola  Inc SN54LS112A
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16 9
-B-
P 0.25 (0.010) M
BM
1
8 PL
8
G
-T-
D16 PL
0.25 (0.010) M T B S
AS
C
SEATING
PLANE
K
R X 45°
MF
J
Case 648-08 N Suffix
16-Pin Plastic
-A-
16 9
B
18
F
C
S
-T-
SEATING
PLANE
L
H
G
D 16 PL
K
0.25 (0.010) M T A M
J
M
Case 620-09 J Suffix
-A- 16-Pin Ceramic Dual In-Line
16 9
-B-
18
CL
-T-
SEATING
PLANE
F
E
G
D 16 PL
N
0.25 (0.010) M T A S
K
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751BĆ01 IS OBSOLETE, NEW STANDARD
751BĆ03.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0°Ă
0.25
7°Ă
5.80
6.20
0.25
0.50
INCHES
MIN MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0°Ă
0.009
7°Ă
0.229
0.244
0.010
0.019
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
6. 648Ć01 THRU Ć07 OBSOLETE, NEW STANDARD
648Ć08.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MILLIMETERS
MIN MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
0°
7.74
10°
0.51
1.01
INCHES
MIN MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.070
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0°
0.305
10°
0.020
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 620Ć01 THRU Ć08 OBSOLETE, NEW STANDARD
620Ć09.
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MILLIMETERS
MIN MAX
19.05 19.55
6.10
7.36
Ċ 4.19
0.39
0.53
1.27 BSC
1.40
1.77
2.54 BSC
0.23
0.27
Ċ 5.08
7.62 BSC
0° 15°
0.39
0.88
INCHES
MIN MAX
0.750
0.770
0.240
0.290
Ċ 0.165
0.015
0.021
0.050 BSC
0.055
0.070
0.100 BSC
0.009
0.011
Ċ 0.200
0.300 BSC
0° 15°
0.015
0.035
FAST AND LS TTL DATA
5-187







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