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SHIFT REGISTER. SN54LS164 Datasheet |
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SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis-
ter. Serial data is entered through a 2-Input AND gate synchronous with the
LOW to HIGH transition of the clock. The device features an asynchronous
Master Reset which clears the register setting all outputs LOW independent of
the clock. It utilizes the Schottky diode clamped process to achieve high
speeds and is fully compatible with all Motorola TTL products.
• Typical Shift Frequency of 35 MHz
• Asynchronous Master Reset
• Gated Serial Data Input
• Fully Synchronous Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q7 Q6 Q5 Q4 MR CP
14 13 12 11 10 9 8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1234567
A B Q0 Q1 Q2 Q3 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A, B
CP
MR
Q0 – Q7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS164
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
1A
LS164
2 B 8-BIT SHIFT REGISTER
8 CP
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
9 3 4 5 6 10 11 12 13
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-1
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SN54 / 74LS164
A
1
2
B
8 CP
DQ
CD
DQ
CD
LOGIC DIAGRAM
DQ
CD
DQ
CD
DQ
CD
DQ
CD
DQ
CD
DQ
CD
MR
9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = PIN 14
3
4
5 6 10 11 12 13
GND = PIN 7
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages. Data
is entered serially through one of two inputs (A or B); either of
these inputs can be used as an active HIGH Enable for data
entry through the other input. An unused input must be tied
HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical AND
of the two data inputs (A•B) that existed before the rising clock
edge. A LOW level on the Master Reset (MR) input overrides
all other inputs and clears the register asynchronously, forcing
all Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATING
MODE
Reset (Clear)
INPUTS
MR A
LX
B
X
OUTPUTS
Q0 Q1–Q7
L L–L
Shift
H I I L q0 – q6
H I h L q0 – q6
H h I L q0 – q6
H h h H q0 – q6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don’t Care
qn = Lower case letters indicate the state of the referenced input or output one
qn = set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
FAST AND LS TTL DATA
5-2
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SN54 / 74LS164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65
– 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIH or VIL
V
IOL = 8.0 mA
per Truth Table
IIH Input HIGH Current
20
0.1
IIL Input LOW Current
– 0.4
IOS Short Circuit Current (Note 1)
– 20
–100
ICC Power Supply Current
27
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
mA VCC = MAX
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay
MR to Output Q
Propagation Delay
Clock to Output Q
Limits
Min Typ Max
25 36
24 36
17 27
21 32
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
CP, MR Pulse Width
Data Setup Time
Data Hold Time
MR to Clock Recovery Time
Limits
Min Typ Max
20
15
5.0
20
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-3
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