SN54LS173A OUTPUTS Datasheet

SN54LS173A Datasheet, PDF, Equivalent


Part Number

SN54LS173A

Description

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

Manufacture

Motorola Inc

Total Page 6 Pages
Datasheet
Download SN54LS173A Datasheet


SN54LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either
Output Enable line (OE1, OE2) brings the output to a high impedance state
without affecting the actual register contents. A HIGH on the Master Reset
(MR) input resets the Register regardless of the state of the Clock (CP), the
Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines.
Fully Edge-Triggered
3-State Outputs
Gated Input and Output Enables
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC MR D0 D1 D2 D3 IE2 IE1
16 15 14 13 12 11 10 9
1 2 3 4 56
OE1 OE2 Q0 Q1 Q2 Q3
78
CP GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D3
IE1 – IE2
OE1 – OE2
CP
MR
Q0 – Q3
Data Inputs
Input Enable (Active LOW)
Output Enable (Active LOW) Inputs
Clock Pulse (Active HIGH Going Edge)
Input
Master Reset Input (Active HIGH)
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
65 (25) U.L. 15 (7.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
9 10 14 13 12 11
12
7
11
22
IE
CP
OE
MR
D0 D1 D2 D3
Q0 Q1 Q2Q3
15 3 4 5 6
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-316

SN54LS173A
LOGIC DIAGRAM
IE1 9
IE2 10
SN54 / 74LS173A
D0
14
D1
13
D2
12
D3
11
CP
7
MR 15
OE1 1
OE2 2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
CP D
QQ
3
Q0
D
4
Q1
DD
5
Q2
6
Q3
TRUTH TABLE
MR CP IE1 IE2 Dn Qn
Hx xxxL
L L x x x Qn
L H x x Qn
L x H x Qn
L LLLL
L L L HH
When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance);
however this does not affect the contents or sequential operation of the register.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54
– 1.0
mA
74 – 2.6
54 12 mA
74 24
FAST AND LS TTL DATA
5-317


Features SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organize d systems. The clock is fully edge-trig gered allowing either a load from the D inputs or a hold (retain register cont ents) depending on the state of the Inp ut Enable Lines (IE1, IE2). A HIGH on e ither Output Enable line (OE1, OE2) bri ngs the output to a high impedance stat e without affecting the actual register contents. A HIGH on the Master Reset ( MR) input resets the Register regardles s of the state of the Clock (CP), the O utput Enable (OE1, OE2) or the Input En able (IE1, IE2) lines. • Fully Edge-T riggered • 3-State Outputs • Gated Input and Output Enables • Input Clam p Diodes Limit High-Speed Termination E ffects 16 1 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 MR 15 D0 14 D1 13 D2 12 D3 11 IE2 10 IE1 9 NOTE: The Flatpak version has the sam.
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