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D FLIP-FLOP. SN54LS175 Datasheet |
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QUAD D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
1 2 3 4 56
78
MR Q0 Q0 D0 D1 Q1 Q1 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs (Note b)
Complemented Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
MR CP D3
1 9 13
D2
12
D1
5
D0
4
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
VCC = PIN 16
GND = PIN 8
14 15
Q3 Q3
= PIN NUMBERS
11 10
Q2 Q2
67
Q1Q1
32
Q0 Q0
SN54/74LS175
QUAD D FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4 5 12
13
D0 D1 D2 D3
9 CP
1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
3 2 6 7 11 10 14 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-327
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SN54 / 74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops with
individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW to HIGH Clock
(CP) transition, causing individual Q and Q outputs to follow. A
LOW input on the Master Reset (MR) will force all Q outputs
LOW and Q outputs HIGH independent of Clock or Data
inputs.
The LS175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D QQ
LL
HH
Note 1: t = n + 1 indicates conditions after next clock.
H
L
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
18
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
FAST AND LS TTL DATA
5-328
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SN54 / 74LS175
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
30 40
20 30
20 30
13 25
16 25
Unit
MHz
ns
ns
Limits
Min Typ Max
20
20
5.0
25
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
AC WAVEFORMS
CP
D
Q
Q
1.3 V
ts(H)
* 1.3 V
1/fmax
tw
ts(L)
th(H)
1.3 V
tPLH
1.3 V
tPHL
1.3 V
1.3 V
th(L)
1.3 V
tPHL
1.3 V
tPLH
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
MR
CP
Q
Q
tPLH
tW
1.3 V
1.3 V
trec
1.3 V
tPHL
1.3 V
1.3 V
1.3 V
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-329
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