SHIFT REGISTER. SN54LS194A Datasheet

SN54LS194A REGISTER. Datasheet pdf. Equivalent

SN54LS194A Datasheet
Recommendation SN54LS194A Datasheet
Part SN54LS194A
Description 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
Feature SN54LS194A; SN54/74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The SN54 / 74LS194A is a High Speed 4-Bit.
Manufacture Motorola Inc
Datasheet
Download SN54LS194A Datasheet




Motorola  Inc SN54LS194A
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift
Register. As a high speed multifunctional sequential building block, it is useful
in a wide variety of applications. It may be used in serial-serial, shift left, shift
right, serial-parallel, parallel-serial, and parallel-parallel data register trans-
fers. The LS194A is similar in operation to the LS195A Universal Shift
Register, with added features of shift left without external connections and
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped
process to achieve high speeds and is fully compatible with all Motorola TTL
families.
Typical Shift Frequency of 36 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q0 Q1 Q2 Q3 CP S1 S0
16 15 14 13 12 11 10 9
1 2 3 4 56 78
MR DSR P0 P1 P2 P3 DSL GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
S0, S1
P0 – P3
DSR
DSL
CP
MR
Q0 – Q3
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS194A
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-360



Motorola  Inc SN54LS194A
LOGIC DIAGRAM
10
S1
9
S0
2
DSR
P0
3
SN54 / 74LS194A
P1 P2
45
P3
6
7
DSL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
11
CP
1
MR
S Q0
CP
R
CLEAR
15
Q0
S Q1
CP
R
CLEAR
14
Q1
S Q2
CP
R
CLEAR
13
Q2
S Q3
CP
R
CLEAR
12
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS194A 4-Bit Bidirectional Shift Regis-
ter. The LS194A is similar in operation to the Motorola LS195A
Universal Shift Register when used in serial or parallel data
register transfers. Some of the common features of the two
devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations taking
place in less than 15 ns (typical) making the device especially
useful for implementing very high speed CPUs, or the memory
buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing on
P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
Q3 outputs respectively following the next LOW to HIGH
transition of the clock.
The asynchronous Master Reset (MR), when LOW, over-
rides all other input conditions and forces the Q outputs LOW.
Special logic features of the LS194A design which increase
the range of application are described below:
Two mode control inputs (S0, S1) determine the synchro-
nous operation of the device. As shown in the Mode Selection
Table, data can be entered and shifted from left to right (shift
right, Q0 Q1, etc.) or right to left (shift left, Q3 Q2, etc.), or
parallel data can be entered loading all four bits of the register
simultaneously. When both S0 and S1,are LOW, the existing
data is retained in a “do nothing” mode without restricting the
HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift left
data transfers without interfering with parallel load operation.
MODE SELECT — TRUTH TABLE
OPERATING MODE
Reset
MR S1
LX
INPUTS
S0 DSR
XX
OUTPUTS
DSL Pn Q0 Q1 Q2
X X LL L
Q3
L
Hold
HI
I
X
X
X
q0 q1
q2
q3
Shift Left
Hh
I
X
I
X
q1 q2
q3
Hh
I
X
h
X
q1 q2
q3
L
H
Shift Right
HIh
HIh
I
h
X X L q0 q1
X X H q0 q1
q2
q2
Parallel Load
Hh h
X
X Pn P0 P1 P2
P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
FAST AND LS TTL DATA
5-361



Motorola  Inc SN54LS194A
SN54 / 74LS194A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
Guaranteed Input HIGH Voltage for
V All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
– 0.65 – 1.5
V VCC = MIN, IIN = – 18 mA
Output HIGH Voltage
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
IIH Input HIGH Current
20
0.1
IIL Input LOW Current
– 0.4
IOS Short Circuit Current (Note 1) – 20
– 100
ICC Power Supply Current
23
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
mA VCC = MAX
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Propagation Delay,
MR to Output
Limits
Min Typ Max
25 36
14 22
17 26
19 30
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
FAST AND LS TTL DATA
5-362







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