RIPPLE COUNTERS. SN54LS196 Datasheet

SN54LS196 COUNTERS. Datasheet pdf. Equivalent

SN54LS196 Datasheet
Recommendation SN54LS196 Datasheet
Part SN54LS196
Description 4-STAGE PRESETTABLE RIPPLE COUNTERS
Feature SN54LS196; 4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-tw.
Manufacture Motorola Inc
Datasheet
Download SN54LS196 Datasheet




Motorola  Inc SN54LS196
4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
Low Power Consumption — Typically 80 mW
High Counting Rates — Typically 70 MHz
Choice of Counting Modes — BCD, Bi-Quinary, Binary
Asynchronous Presettable
Asynchronous Master Reset
Easy Multistage Cascading
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC MR Q3 P3 P1 Q1 CP0
14 13 12 11 10 9
8
1234567
PL Q2 P2 P0 Q0 CP1 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP0
Clock (Active LOW Going Edge)
1.0 U.L.
1.5 U.L.
Input to Divide-by-Two Section
CP1 (LS196) Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
2.0 U.L.
1.75 U.L.
CP1 (LS197) Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
1.0 U.L.
0.8 U.L.
MR
Master Reset (Active LOW) Input
1.0 U.L.
0.5 U.L.
PL
Parallel Load (Active LOW) Input
0.5 U.L.
0.25 U.L.
P0–P3
Q0–Q3
Data Inputs
Outputs (Notes b, c)
0.5 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
FAST AND LS TTL DATA
5-372
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
1 4 10 3 11
8 CP0 PL P0 P1 P2 P3
6 CP1 MR Q0 Q1 Q2 Q3
13 5 9 2 12
VCC = PIN 14
GND = PIN 7



Motorola  Inc SN54LS196
SN54/74LS196 SN54/74LS197
LOGIC DIAGRAM
13
MR
PL
1
8
CP0
6
CP1
P0
4
P1
10
P2
3
P3
11
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
5
Q0
LS196
9
Q1
2
Q2
12
Q3
13
MR
PL
1
P0
4
P1
10
P2
3
P3
11
8
CP0
6
CP1
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
5
Q0
LS197
9
Q1
2
Q2
12
Q3
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
FAST AND LS TTL DATA
5-373



Motorola  Inc SN54LS196
SN54/74LS196 SN54/74LS197
FUNCTIONAL DESCRIPTION
The LS196 and LS197 are asynchronously presettable de-
cade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divide-
by-eight sections, with all sections having a separate Clock in-
put. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to de-
code the Q outputs, designers should bear in mind that the un-
equal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP0 input
serves the Q0 flip-flop in both circuit types while the CP1 input
serves the divide-by-five or divide-by-eight section. The Q0
output is designed and specified to drive the rated fan-out plus
the CP1 input. With the input frequency connected to CP0 and
Q0 driving CP1, the LS197 forms a straightforward module-16
counter, with Q0 the least significant output and Q3 the most
significant output.
The LS196 Decade Counter can be connected up to oper-
ate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP0 and
with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP1 and Q3
driving CP0, Q0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
The LS196 and LS197 have an asynchronous active LOW
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P0 – P3)
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the Pn inputs will be re-
flected in the outputs.
Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1)
BI-QUINARY (NOTE 2)
COUNT Q3 Q2
0 LL
1 LL
2 LL
3 LL
4 LH
5 LH
6 LH
7 LH
8 HL
9 HL
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.
Q1
L
L
H
H
L
L
H
H
L
L
Q0 COUNT
L0
H1
L2
H3
L4
H5
L6
H7
L8
H9
Q0
L
L
L
L
L
H
H
H
H
H
Q3 Q2
LL
LL
LH
LH
HL
LL
LL
LH
LH
HL
Q1
L
H
L
H
L
L
H
L
H
L
MODE SELECT TABLE
INPUTS
MR PL
CP
RESPONSE
LX
HL
HH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
X
X
Reset (Clear)
Parallel Load
Count
FAST AND LS TTL DATA
5-374







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