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ADDRESSABLE LATCH. SN54LS256 Datasheet |
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DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A0, A1), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q0 – Q3).
When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs
(Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and
E are both LOW. When CL is HIGH and E is LOW, the selected output
(Q0 – Q3), determined by the Address inputs, follows D. When the E goes
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address
(A0, A1) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E= CL = HIGH).
• Serial-to-Parallel Capability
• Output From Each Storage Bit Available
• Random (Addressable) Data Entry
• Easily Expandable
• Active Low Common Clear
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CL E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
12
A0 A1
3 4 56 78
Da Q0a Q1a Q2a Q3a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Da, Db
E
Address Inputs
Data Inputs
Enable Input (Active LOW)
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
CL Clear Input (Active LOW)
0.5 U.L.
0.25 U.L.
Q0a – Q3a,
Q0b – Q3b
Parallel Latch Outputs (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3
2 1 15
14 13
Da E
A0
A1
CL
Q0a Q1a Q2a Q3a
A0 E Db
A1
CL
Q0b Q1b Q2b Q3b
4 56 7
9 10 11 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-421
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LOGIC DIAGRAM
E
14
Da
3
A0
1
SN54 / 74LS256
A1
2
CL
15
Db
13
4
Q0a
5
Q1a
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
6
Q2a
CL E
LH
LL
LL
LL
LL
LL
LL
LL
LL
HH
HL
HL
HL
HL
HL
HL
HL
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
D
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
E
L
H
L
H
7
Q3a
9
Q0b
10
Q1b
TRUTH TABLE
A0 A1 Q0 Q1 Q2
XXL L L
LLLLL
L LHL L
HL L L L
HL LHL
LHL L L
LHL LH
HHL L L
HHL L L
X X QN–1 QN–1 QN–1
L L L QN–1 QN–1
L L H QN–1 QN–1
H L QN–1 L QN–1
H L QN–1 H QN–1
L H QN–1 QN–1 L
L H QN–1 QN–1 H
H H QN–1 QN–1 QN–1
H H QN–1 QN–1 QN–1
MODE SELECTION
CL MODE
H Addressable Latch
H Memory
L Dual 4-Channel Demultiplexer
L Clear
11
Q2b
12
Q3b
Q3
L
L
L
L
L
L
L
L
H
QN–1
QN–1
QN–1
QN–1
QN–1
QN–1
QN–1
L
H
MODE
Clear
Demultiplex
Memory
Addressable
Latch
FAST AND LS TTL DATA
5-422
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SN54 / 74LS256
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
Guaranteed Input HIGH Voltage for
V All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
VOL
Input Clamp Diode Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
Output HIGH Voltage
54, 74 2.4
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
Input HIGH Current
Others
IIH E Input
Others
E Input
20 µA VCC = MAX, VIN = 2.7 V
40
0.1
0.2
mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL Others
E Input
– 0.4
– 0.8
mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
30
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C)
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Turn-Off Delay, Enable to Output
Turn-On Delay, Enable to Output
Turn-Off Delay, Data to Output
Turn-On Delay, Data to Output
Turn-Off Delay, Address to Output
Turn-On Delay, Address to Output
Turn-On Delay, Clear to Output
Limits
Min Typ Max
20 27
16 24
20 30
13 20
20 30
14 24
12 23
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 3
Figure 5
VCC = 5.0 V,
CL = 15 pF
FAST AND LS TTL DATA
5-423
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