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SN54LS256 Datasheet, Equivalent, ADDRESSABLE LATCH.DUAL 4-BIT ADDRESSABLE LATCH DUAL 4-BIT ADDRESSABLE LATCH |
| Part | SN54LS256 |
|---|---|
| Description | DUAL 4-BIT ADDRESSABLE LATCH |
| Feature | SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATC H
The SN54/74LS256 is a Dual 4-Bit Addr essable Latch with common control input s; these include two Address inputs (A0 , A1), an active LOW Enable input (E) a nd an active LOW Clear input (CL). Each latch has a Data input (D) and four ou tputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW , all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when t he (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH , the contents of th . |
| Manufacture | Motorola Inc |
| Datasheet |
| Part | SN54LS256 |
|---|---|
| Description | DUAL 4-BIT ADDRESSABLE LATCH |
| Feature | SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATC H
The SN54/74LS256 is a Dual 4-Bit Addr essable Latch with common control input s; these include two Address inputs (A0 , A1), an active LOW Enable input (E) a nd an active LOW Clear input (CL). Each latch has a Data input (D) and four ou tputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW , all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when t he (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH , the contents of th . |
| Manufacture | Motorola Inc |
| Datasheet |
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