|
|
BINARY COUNTER. SN54LS290 Datasheet |
|
|
|
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS290 and SN54/ 74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two sec-
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
• Corner Power Pin Versions of the LS90 and LS93
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC MR MR CP1 CP0 Q0 Q3
14 13 12 11 10 9
8
LS290
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1234567
MS NC MS Q2 Q1 NC GND
VCC MR
14 13
MR CP1 CP0
12 11 10
Q0
9
Q3
8
LS293
SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1234567
NC NC NC Q2 Q1 NC GND
PIN NAMES
LOADING (Note a)
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to ÷ 2 Section.
Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).
Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷ 2 Section (Notes b & c)
Outputs from ÷ 5 & ÷ 8 Sections (Note b)
HIGH
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
FAST AND LS TTL DATA
5-466
|
SN54/74LS290 D SN54/74LS293
LOGIC SYMBOL
LS290
13
10
11
12
MS
CP0
CP1
MR
Q0 Q1 Q2 Q3
12
12 13
9 548
VCC = PIN 14
GND = PIN 7
NC = PINS 2, 6
LS293
10
11
CP0
CP1
MR
Q0 Q1 Q2 Q3
12
12 13
9 548
VCC = PIN 14
GND = PIN 7
NC = PINS 1, 2, 3, 6
LOGIC DIAGRAMS
MS1
MS2
1
3
CP0
10
SD
JQ
CP
Q
CD
LS290
JQ
CP
KQ
CD
JQ
CP
KQ
CD
SD
RQ
CP
SQ
CD
11
CP1
MR1
12
MR2
13
9
Q0
5
Q1
4
Q2
8
Q3
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
LS293
CP0
10
JQ
CP
KQ
CD
CP1
MR1
MR2
11
12
13
9
Q0
JQ
CP
KQ
CD
JQ
CP
KQ
CD
JQ
CP
KQ
CD
5
Q1
4
Q2
8
Q3
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
FAST AND LS TTL DATA
5-467
|
SN54/74LS290 D SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/ slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1 ⋅ MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 ⋅ MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous division of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
LS290 MODE SELECTION
RESET/SET INPUTS
OUTPUTS
MR1
H
H
X
L
X
L
X
MR2
H
H
X
X
L
X
L
MS1
L
X
H
L
X
X
L
MS2
X
L
H
X
L
L
X
Q0 Q1 Q2
LLL
LLL
HL L
Count
Count
Count
Count
Q3
L
L
H
LS290
BCD COUNT SEQUENCE
OUTPUT
COUNT
Q0 Q1 Q2
0
LL
L
1
HL
L
2
LH
L
3
HH
L
4
LL
H
5
HL
H
6 LH H
7 HH H
8
LL
L
9
HL
L
Q3
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS293 MODE SELECTION
RESET INPUTS
OUTPUTS
MR1
H
L
H
L
MR2
H
H
L
L
Q0 Q1 Q2
LLL
Count
Count
Count
Q3
L
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TRUTH TABLE
OUTPUT
Q0 Q1
LL
HL
LH
HH
LL
HL
LH
HH
LL
HL
LH
HH
LL
HL
LH
HH
Q2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Note: Output Q0 connected to input CP1.
Q3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
FAST AND LS TTL DATA
5-468
|
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |