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SHIFT REGISTERS. SN54LS322A Datasheet |
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8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
These 8-bit shift registers have multiplexed input/output data ports to
accomplish full 8-bit data handling in a single 20-pin package. Serial data may
enter the shift-right register through either D0 or D1 inputs as selected by the
data select pin. A serial output is also provided. Synchronous parallel loading
is achieved by taking the register enable and the S / P inputs low. This places
the three-state input / output ports in the data input mode. Data is entered on
the low-to-high clock transition. The data extend function repeats the sign in
the QA flip-flop during shifting. An overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the register.
• Multiplexed Inputs/ Outputs Provide Improved Bit Density
• Sign Extend Function
• Direct Overriding Clear
• 3-State Outputs Drive Bus Lines Directly
(TOP VIEW)
DATA SIGN
VCC SELECT EXTEND D1
20 19 18 17
B/QB D/QD F/QF H/QH
16 15 14 13
Q/H CLOCK
12 11
DS SE D1 B/QB D/QD F/QF H/GH Q/H
G CK
S/P D0 A/QA C/QC E/QE G/QG OE CLR
12
REGISTER S/P
ENABLE
3 4 5 6 7 8 9 10
D0 A/QA C/QC E/QE G/QG OUTPUT CLEAR GND
ENABLE
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH
Output Current — High
QH′
IOL
Output Current — Low
QH′
QH′
IOH
Output Current — High
QA– QH
QA– QH
IOL
Output Current — Low
QA– QH
QA– QH
54
74
54
74
54, 74
54
74
54
74
54
74
SN54/74LS322A
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Min Typ Max Unit
4.5 5.0 5.5
4.75 5.0 5.25
V
– 55 25 125 °C
0 25 70
– 0.4
mA
4.0 mA
8.0
– 1.0
– 2.6
mA
12 mA
24
FAST AND LS TTL DATA
5-1
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SN54 / 74LS322A
REGISTER
ENABLE
G
S/P
(1)
(2)
SIGN
EXTEND
SE
DATA D1
SELECT
DS
D0
(18)
(17)
(19)
(3)
CLOCK (11)
CLEAR (9)
OUTPUT
ENABLE
OE
(8)
BLOCK DIAGRAM
Q
CK
DQ
CLR
Q
CK
DQ
CLR
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
Q
CK
DQ
CLR
Q
CK
DQ
CLR
(12)
QH
(4)
A/QA
(16)
B/QB
(7)
G/QG
(13)
H/QH
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
OPERATION
CLEAR
REGISTER
ENABLE
S/P
SIGN
EXTEND
DATA
SELECT
OUTPUT
ENABLE
CLOCK
A/QA B/QB C/QC … H/QH
OUTPUT
QH′
Clear
L
L
H XX
X HX
X
X
L
X LLL L
L
L
X LLL L
L
Hold
Shift Right
Sign Extend
Load
H
H
H
H
H
H XX
L HH
L HH
L HL
L LX
X
L
H
X
X
L
X
QA0 QB0 QC0 QH0
QH0
L
↑
D0 QAn QBn QGn
QGn
L
↑
D1 QAn QBn QGn
QGn
L
↑
QAn QAn QBn QGn
QGn
X
↑ abc h
h
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is
cleared while the eight input/output terminals are disabled to the high-impedance state.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW to HIGH level
QA0…QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established
QAn…QHn = the level of QA through QH, respectively, before the most recent ↑ transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a…h = the level of steady-state inputs at inputs A through H respectively
FAST AND LS TTL DATA
5-2
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SN54 / 74LS322A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
QA– QH
54
74
– 0.65 – 1.5
2.4 3.2
2.4 3.2
V VCC = MIN, IIN = – 18 mA
V
VCC = MIN, IOH = MAX
V
VOH
Output HIGH Voltage
QH′
54 2.5 3.4
74 2.7 3.4
V
V VCC = MIN, IOH = MAX
VOL
Output LOW Voltage
QA– QH
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 12 mA
V IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
QH′
54, 74
74
0.4
V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
0.5
V IOL = 8.0 mA
per Truth Table
IOZH
IOZL
Output Off Current HIGH
QA– QH
Output Off Current LOW
QA– QH
Other
40 µA VCC = MAX, VOUT = 2.7 V
– 400 µA VCC = MAX, VOUT = 0.4 V
20 µA
A – H,
Data Select
40 µA VCC = MAX, VIN = 2.7 V
Sign Extend
IIH
Input HIGH Current
Other
60 µA
0.1 mA
Data Select
Sign Extend
0.2 mA VCC = MAX, VIN = 7.0 V
0.3 mA
A–H
Other
0.1
– 0.4
mA VCC = MAX, VIN = 5.5 V
mA
IIL Input LOW Current Data Select
Sign Extend
– 0.8
– 1.2
mA VCC = MAX, VIN = 0.4 V
mA
Short Circuit Current QH′
IOS (Note 1)
QA– QH
– 20
– 30
–100 mA VCC = MAX
–130 mA VCC = MAX
ICC Power Supply Current
60
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
FAST AND LS TTL DATA
5-3
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