4-INPUT MULTIPLEXER. SN54LS353 Datasheet

SN54LS353 MULTIPLEXER. Datasheet pdf. Equivalent

SN54LS353 Datasheet
Recommendation SN54LS353 Datasheet
Part SN54LS353
Description DUAL 4-INPUT MULTIPLEXER
Feature SN54LS353; SN54/74LS353 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL/ MSI SN54/ 74LS353 is a Dual 4-.
Manufacture Motorola Inc
Datasheet
Download SN54LS353 Datasheet




Motorola  Inc SN54LS353
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
The LSTTL/ MSI SN54/ 74LS353 is a Dual 4-Input Multiplexer with 3-state
outputs. It can select two bits of data from four sources using common select
inputs. The outputs may be individually switched to a high impedance state
with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs
to interface directly with bus oriented systems. It is fabricated with the Schott-
ky barrier diode process for high speed and is completely compatible with all
TTL families.
Inverted Version of the SN54 / 74LS253
Schottky Process for High Speed
Multifunction Capability
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC E0b
16 15
S0
14
I3b I2b I1b
13 12 11
I0b Zb
10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56
78
E0a S1 I3a I2a I1a I0a Za GND
PIN NAMES
S0, S1
Common Select Inputs
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.25 U.L.
Multiplexer A
E0a
I0A – I3a
Za
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output (Note b)
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
Multiplexer B
E0b
I0b – I3b
Zb
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output (Note b)
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military and 65 U.L.
for Commercial Temperature Ranges.
SN54/74LS353
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
1 6 5 4 3 10 11 12 13 15
E0a I0a I1a I2a I3a I0b I1b I2b I3b E0b
14 S0
2 S1
Za
Zb
79
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-510



Motorola  Inc SN54LS353
SN54 / 74LS353
LOGIC DIAGRAM
E0b
15
I3b
13
I2b
12
I1b
11
I0b
10
S0 S1
14 2
I3a I2a I1a I0a E0a
34 56 1
VCC = PIN 16
9 GND = PIN 8
7
Zb
= PIN NUMBERS
Za
FUNCTIONAL DESCRIPTION
The SN54 / 74LS353 contains two identical 4-input Multi-
plexers with 3-state outputs. They select two bits from four
sources selected by common select inputs (S0, S1). The
4-input multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The logic equations for the outputs are shown below:
Za = E0a (I0a S1 S0 + I1a S1 S0 + I2a S1 S0 + I3a S1 S0)
Zb = E0b (I0b S1 S0 + I1b S1 S0 + I2b S1 S0 + I3b S1 S0)
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
TRUTH TABLE
SELECT
INPUTS
DATA INPUTS
S0 S1
I0
I1
I2
XXXXX
L L LXX
L LHXX
HLXLX
H L XHX
L HXX L
LHXXH
HHXXX
HHXXX
I3
X
X
X
X
X
X
X
L
H
H = HIGH Level
L = LOW Level
X = Immaterial
(Z) = High Impedance (off)
Address inputs S0 and S1 are common to both sections.
OUTPUT
ENABLE
E0
H
L
L
L
L
L
L
L
L
OUTPUT
Z
(Z)
H
L
H
L
H
L
H
L
FAST AND LS TTL DATA
5-511



Motorola  Inc SN54LS353
SN54 / 74LS353
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 –55 25 125 °C
74 0 25 70
54
– 1.0
mA
74 –2.6
54 12 mA
74 24
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5
2.4 3.4
2.4 3.1
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
QA – QH
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 12 mA
V IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IOZH
Output Off Current HIGH
20 µA VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current LOW
– 20 µA VCC = MAX, VOUT = 0.4 V
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 130 mA VCC = MAX
Power Supply Current
ICC Total, Output 3-State
Total, Output LOW
14 mA VCC = MAX
12
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tPLH
tPHL
tPLH
tPHL
tPZH
Propagation Delay,
Data to Output
Propagation Delay,
Select to Output
Output Enable Time
to HIGH Level
11
13
25
20
ns
Figure 1
20 45
21 32
ns
Figure 1 or 2
11 23 ns
Figures 4, 5
CL = 15 pF
tPZL
Output Enable Time
to LOW Level
15 23 ns
Figures 3, 5
tPLZ
tPHZ
Output Disable Time
to LOW Level
Output Disable Time
to HIGH Level
12 27 ns
27 41 ns
Figures 3, 5
Figures 4, 5
CL = 5.0 pF
FAST AND LS TTL DATA
5-512







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