|
|
D FLIP-FLOP. SN54LS377 Datasheet |
|
|
|
OCTAL D FLIP-FLOP WITH ENABLE;
HEX D FLIP-FLOP WITH ENABLE;
4-BIT D FLIP-FLOP WITH ENABLE
The SN54 / 74LS377 is an 8-bit register built using advanced Low Power
Schottky technology. This register consists of eight D-type flip-flops with a
buffered common clock and a buffered common clock enable.
The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable.
This device is similar to the SN54 / 74LS174, but with common Enable rather
than common Master Reset.
The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This
device is similar to the SN54 / 74LS175 but features the common Enable
rather then common Master Reset.
• 8-Bit High Speed Parallel Registers
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
HIGH
LOW
E Enable (Active LOW) Input
0.5 U.L.
0.25 U.L.
D0 – D3
CP
Data Inputs
Clock (Active HIGH Going Edge) Input
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
Q0 – Q3
Q0 – Q3
True Outputs (Note b)
Complemented Outputs (Note b)
10 U.L.
10 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS377
SN54/74LS378
SN54/74LS379
OCTAL D FLIP-FLOP WITH
ENABLE; HEX D FLIP-FLOP
WITH ENABLE; 4-BIT D FLIP-FLOP
WITH ENABLE
LOW POWER SCHOTTKY
20
1
20
1
20
1
16
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN74LSXXXD SOIC
FAST AND LS TTL DATA
5-533
|
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
CONNECTION DIAGRAM DIPS (TOP VIEW)
SN54 / 74LS377
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 5 6 7 8 9 10
E Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
SN54 / 74LS378
VCC Q5 D5 D4 Q4 D3 Q3 CP
16 15 14 13 12 11 10 9
1 2 3 4 56
78
E Q0 D0 D1 Q1 D2 Q2 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54 / 74LS379
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
1 2 3 4 56
78
E Q0 Q0 D0 D1 Q1 Q1 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-534
|
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
SN54 / 74LS377
E
ENABLE
1
3
D0
4
D1
LOGIC DIAGRAMS
7 8 13
D2 D3 D4
14 17
D5 D6
18
D7
CP
CLOCK
11
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
SN54 / 74LS378
Q0
2
CP
9
1
E
SN54 / 74LS379
CP
9
1
E
Q1 Q2 Q3 Q4
5 6 9 12
34
6 11
D0 D1 D2 D3
Q5 Q6
15 16
13 14
D4 D5
CP D
E
Q
CP D
E
Q
CP D
E
Q
CP D
E
Q
CP D
E
Q
CP D
E
Q
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
45
D0 D1
12 13
D2 D3
CP
E
Q
D
Q
CP
E
Q
D
Q
CP
E
Q
D
Q
CP
E
Q
D
Q
Q0 Q0
32
Q1 Q1
67
Q2 Q2
11 10
Q3 Q3
14 15
Q7
19
FAST AND LS TTL DATA
5-535
|
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |