BINARY COUNTER. SN54LS390 Datasheet 


DUAL DECADE COUNTER;
DUAL 4STAGE
BINARY COUNTER
The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of highspeed
4stage ripple counters. Each half of the LS390 is partitioned into a
dividebytwo section and a divideby five section, with a separate clock input
for each section. The two sections can be connected to count in the 8.4.2.1
BCD code or they can count in a biquinary sequence to provide a square wave
(50% duty cycle) at the final output.
Each half of the LS393 operates as a Modulo16 binary divider, with the last
three stages triggered in a ripple fashion. In both the LS390 and the LS393,
the flipflops are triggered by a HIGHtoLOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a
HIGH signal by forcing all four outputs to the LOW state.
• Dual Versions of LS290 and LS293
• LS390 has Separate Clocks Allowing ÷ 2, ÷ 2.5, ÷ 5
• Individual Asynchronous Clear for Each Counter
• Typical Max Count Frequency of 50 MHz
• Input Clamp Diodes Minimize High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54 / 74LS390
VCC CP0 MR Q0 CP1 Q1 Q2 Q3
16 15 14 13 12 11 10 9
1 2 3 4 56
CP0 MR Q0 CP1 Q1 Q2
78
Q3 GND
SN54 / 74LS393
VCC CP MR Q0 Q1 Q2 Q3
14 13 12 11 10 9
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual InLine Package.
1234567
CP MR Q0 Q1 Q2 Q3 GND
SN54/74LS390
SN54/74LS393
DUAL DECADE COUNTER;
DUAL 4STAGE
BINARY COUNTER
LOW POWER SCHOTTKY
16
1
16
1
16
1
14
1
14
1
14
1
J SUFFIX
CERAMIC
CASE 62009
N SUFFIX
PLASTIC
CASE 64808
D SUFFIX
SOIC
CASE 751B03
J SUFFIX
CERAMIC
CASE 63208
N SUFFIX
PLASTIC
CASE 64606
D SUFFIX
SOIC
CASE 751A02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5544

SN54/74LS390 • SN54/74LS393
PIN NAMES
LOADING (Note a)
CP
CP0
CP1
MR
Q0 – Q3
Clock (Active LOW going edge)
Input to +16 (LS393)
Clock (Active LOW going edge)
Input to ÷ 2 (LS390)
Clock (Active LOW going edge)
Input to ÷ 5 (LS390)
Master Reset (Active HIGH) Input
FlipFlop outputs (Note b)
HIGH
LOW
0.5 U.L.
1.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
1.5 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b) Temperature Ranges.
FUNCTIONAL DESCRIPTION
Each half of the SN54 / 74LS393 operates in the Modulo 16
binary sequence, as indicated in the ÷ 16 Truth Table. The first
flipflop is triggered by HIGHtoLOW transitions of the CP
input signal. Each of the other flipflops is triggered by a
HIGHtoLOW transition of the Q output of the preceding
flipflop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flipflops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
Each half of the LS390 contains a ÷ 5 section that is
independent except for the common MR function. The ÷ 5
section operates in 4.2.1 binary sequence, as shown in the ÷ 5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a ÷10
function having a 50% duty cycle output, connect the input
signal to CP1 and connect the Q3 output to the CP0 input; the
Q0 output provides the desired 50% duty cycle output. If the
input frequency is connected to CP0 and the Q0 output is
connected to CP1, a decade divider operating in the 8.4.2.1
BCD code is obtained, as shown in the BCD Truth Table. Since
the flipflops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
SN54 / 74LS390 LOGIC DIAGRAM (one half shown)
CP1
CP0
K CP J
CD Q
K CP J
CD Q
K CP J
CD Q
K CP J
CD Q
MR
Q0 Q1 Q2
SN54 / 74LS393 LOGIC DIAGRAM (one half shown)
CP
Q3
K CP J
CD Q
MR
K CP J
CD Q
K CP J
CD Q
K CP J
CD Q
Q0 Q1
FAST AND LS TTL DATA
5545
Q2
Q3

SN54/74LS390 • SN54/74LS393
SN54 / 74LS390 BCD
TRUTH TABLE
(Input on CP0; Q0 CP1)
COUNT
0
1
2
OUTPUTS
Q3 Q2 Q1 Q0
LLL L
LLLH
L LHL
3 L LHH
4 LHL L
5 LHLH
6 L HH L
7 L HHH
8 HLL L
9 HLLH
SN54/ 74LS390 ÷ 5
TRUTH TABLE
(Input on CP1)
OUTPUTS
COUNT
Q3 Q2 Q1
0 LLL
1 L LH
2 LHL
3 L HH
4 HLL
SN54 / 74LS390 ÷ 10 (50% @ Q0)
TRUTH TABLE
(Input on CP1, Q3 to CP0)
COUNT
0
1
2
OUTPUTS
Q3 Q2 Q1 Q0
LLLL
L LHL
LHL L
3 L HH L
4 HLL L
5 LLLH
6 L LHH
7 LHLH
8 L HHH
9 HLLH
SN54 / 74LS393
TRUTH TABLE
COUNT
0
1
2
3
OUTPUTS
Q3 Q2 Q1 Q0
LLL L
LLLH
L LHL
L LHH
4 LHL L
5 LHLH
6 L HH L
7 L HHH
8 HLL L
9 HLLH
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H
H = HIGH Voltage Level
L = LOW Voltage Level
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
FAST AND LS TTL DATA
5546

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