SHIFT REGISTER. SN54LS395 Datasheet

SN54LS395 REGISTER. Datasheet pdf. Equivalent

SN54LS395 Datasheet
Recommendation SN54LS395 Datasheet
Part SN54LS395
Description 4-BIT SHIFT REGISTER
Feature SN54LS395; SN74LS395 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS The SN74LS395 is a 4-Bit Register with 3-state o.
Manufacture Motorola Inc
Datasheet
Download SN54LS395 Datasheet




Motorola  Inc SN54LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate
in either a synchronous parallel load or a serial shift-right mode, as
determined by the Select input. An asynchronous active LOW Master Reset
(MR) input overrides the synchronous operations and clears the register. An
active HIGH Output Enable (OE) input controls the 3-state output buffers, but
does not interfere with the other operations. The fourth stage also has a
conventional output for linking purposes in multi-stage serial operations.
Shift Left or Parallel 4-Bit Register
3-State Outputs
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC O0 O1 O2 O3 Q3 CP OE
16 15 14 13 12 11 10 9
1 2 3 4 56
MR DS P0 P1 P2 P3
78
S GND
PIN NAMES
P0 – P3
DS
S
CP
MR
OE
O0 – O3
Q3
Parallel Inputs
Serial Data Input
Mode Select Input
Clock (Active LOW) Input
Master Reset (Active LOW) Input
Output Enable (Active HIGH) Input
3-State Register Outputs
Register Output
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
5 U.L.
SN74LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN74LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
734 5 6
S P0 P1 P2 P3
2 DS
10 CP
Q3 11
9 OE
MR O0 O1 O2 O3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-551



Motorola  Inc SN54LS395
LOGIC DIAGRAM
S
Ds
SN 74LS395
P0 P1
P2
P3
CP
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
MR
OE
FUNCTION DESCRIPTION
O0
O1
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
Parallel (Pn) input or from the preceding stage. When the
Select input is HIGH, the Pn inputs are enabled. A LOW signal
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
O2 O3 Q3
S input is LOW, a CP HIGH-LOW transition transfers data in
Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished
by connecting the outputs back to the Pn inputs, but offset one
place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q0 – Q3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still be
accomplished, however.
MODE SELECT — TRUTH TABLE
Operating Mode
Asynchronous Reset
Shift, SET First Stage
Inputs @ tn
Outputs @ tn+1
MR CP
S Ds Pn O0 O1
O2
L X XX X L L L
H L H X H O0n O1n
Shift, RESET First Stage
Parallel Load
H
H
L L X L O0n O1n
H X Pn P0 P1 P2
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
tn, n + 1 = time before and after CP HIGH-to-LOW transition
NOTE:
When OE is HIGH, outputs O0 – O3 are in the high impedance state; however, this does not affect other operations or the Q3 output.
O3
L
O2n
O2n
P3
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Min Typ Max Unit
4.75 5.0 5.25
V
0 25 70 °C
– 0.4
mA
8.0 mA
FAST AND LS TTL DATA
5-552



Motorola  Inc SN54LS395
SN74LS395
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
VOH
VOL
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.7 3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
IOZH
Output Off Current HIGH
20 µA VCC = MAX, VO = 2.4 V
IOZL
Output Off Current LOW
– 20 µA VCC = MAX, VO = 0.4 V
IIH Input HIGH Current
20
– 0.1
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
Power Supply Current
Total, Output HIGH
ICC
Total, Output LOW
31 mA VCC = MAX, OE = GND, CP = GND
34
mA
VCC = MAX, OE = 4.5 V, CP
momentary 3.0 V then GND
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPHL
tPLH
tPHL
tPZH
tPZL
tPLZ
tPHZ
Parameter
Maximum Input Clock Frequency
Propagation Delay, Clear to Output
Propagation Delay, Low to High
Propagation Delay, High to Low
Output Enable Time
Output Disable Time
Limits
Min Typ Max
30 45
22 35
15 30
25 30
15 25
17 25
12 20
11 17
Unit
MHz
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
ts
th
Parameter
Clock Pulse Width
Setup Time, Mode Select
Setup Time, All Others
Data Hold Time
Limits
Min Typ Max
16
40
20
10
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-553







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)