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DECADE COUNTER. SN54LS490 Datasheet |
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DUAL DECADE COUNTER
The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Mas-
ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
• Dual Version of SN54 / 74LS490
• Individual Asynchronous Clear and Preset to 9 for Each Counter
• Count Frequency — Typically 65 MHz
• Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CPb MRb Q0b MSb Q1b Q2b Q3b
16 15 14 13 12 11 10 9
1 2 3 4 56
78
CPa MRa Q0a MSa Q1a Q2a Q3a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
MS
MR
CP
Q0 – Q3
Master Set (Set to 9) Input
Master Reset
Clock Input (Active LOW Going Edge)
Counter Outputs (Note b)
0.5 U.L.
0.5 U.L.
1.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
1.5 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
LOGIC DIAGRAM (ONE HALF SHOWN)
4
MS
12
1
CP 15
2
MR
14
KJ
CD SD
Q
3 Q0 13
KJ
CD
Q
KJ
CD
Q
5 Q1 11
6 Q2 10
K CP J
CD SD
Q
7 Q3 9
SN54/74LS490
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
TRUTH TABLE
OUTPUTS
COUNT
0
1
2
Q3 Q2 Q1
LLL
LLL
L LH
3 LLH
4 LHL
5 LHL
6 LHH
7 LHH
8 HLL
9 HLL
Q0
L
H
L
H
L
H
L
H
L
H
FAST AND LS TTL DATA
5-563
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SN54 / 74LS490
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
Guaranteed Input HIGH Voltage for
V All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.5 3.5
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
IIH
IIL
Output LOW Voltage
Input HIGH Current
Input LOW Current
54, 74
74
MS, MR
Clock
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
– 0.4
–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
26
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
ts
Parameter
Any Pulse Width
MR or MS to Setup Time
Min
20
25
Limits
Typ
Max
Unit
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-564
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SN54 / 74LS490
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay, CP to Q0
Propagation Delay, CP to Q1 or Q3
Propagation Delay, CP to Q2
Propagation Delay, MR to Output
Propagation Delay, MS to Output
Limits
Min Typ Max
25 35
12 20
13 20
24 39
26 39
32 54
36 54
24 39
24 39
20 36
Unit
MHz
ns
ns
ns
ns
ns
AC WAVEFORMS
Test Conditions
Figure 1
Figure 1
Figure 3
Figure 2
Figure 2
Figure 2
VCC = 5.0 V,
CL = 15 pF
*CP 1.3 V
tPHL
Q 1.3 V
tW
Figure 1
1.3 V
tPLH
1.3 V
MR & MS
1.3 V
CP
tPHL
Q
1.3 V
tW trec
1.3 V
1.3 V
Figure 2
MS 1.3 V
CP
QO, Q3
tPLH
1.3 V
tW trec
1.3 V
1.3 V
Figure 3
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the Truth Table.
FAST AND LS TTL DATA
5-565
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