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BUFFER/LINE DRIVER. SN54LS540 Datasheet |
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OCTAL BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
The SN54/ 74LS540 and SN54 / 74LS541 are octal buffers and line drivers
with the same functions as the LS240 and LS241, but with pinouts on the
opposite side of the package.
These device types are designed to be used as memory address drivers,
clock drivers and bus-oriented transmitters / receivers. These devices are
especially useful as output ports for the microprocessors, allowing ease of
layout and greater PC board density.
• Hysteresis at Inputs to Improve Noise Margin
• PNP Inputs Reduce Loading
• 3-State Outputs Drive Bus Lines
• Inputs and Outputs Opposite Side of Package, Allowing Easier
Interface to Microprocessors
• Input Clamp Diodes Limit High-Speed Termination Effects
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW)
SN54 / 74LS540
VCC
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
GND
VCC SN54 / 74LS541
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
GND
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
54
74
54
74
54
74
54
74
SN54/74LS540
SN54/74LS541
OCTAL BUFFER/ LINE DRIVER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Min Typ Max Unit
4.5 5.0 5.5
4.75 5.0 5.25
V
– 55 25 125 °C
0 25 70
– 12 mA
– 15
12 mA
24
FAST AND LS TTL DATA
5-568
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SN54/74LS540 • SN54/74LS541
(1)
E1
(19)
E2
D1
(2)
D2
(3)
D3
(4)
D4
(5)
D5
(6)
D6
(7)
D7
(8)
D8
(9)
LS540
BLOCK DIAGRAM
(1)
E1
(19)
E2
(18)
Y1
(17)
Y2
(16)
Y3
(15)
Y4
(14)
Y5
(13)
Y6
(12)
Y7
(11)
Y8
(2)
D1
(3)
D2
(4)
D3
(5)
D4
(6)
D5
(7)
D6
(8)
D7
(9)
D8
LS541
(18)
Y1
(17)
Y2
(16)
Y3
(15)
Y4
(14)
Y5
(13)
Y6
(12)
Y7
(11)
Y8
INPUTS
OUTPUTS
E1 E2 D LS540
L LH
H XX
X HX
L LL
L
Z
Z
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
LS541
H
Z
Z
L
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
VOL
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
54, 74
54, 74
54, 74
74
– 0.65 – 1.5
2.4 3.4
2.0
0.25 0.4
0.35 0.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = – 3.0 mA
V VCC = MIN, IOH = MAX, VIL = 0.5 V
V IOL = 12 mA
V IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VT+–VT–
IOZH
IOZL
Hysteresis
Output Off Current HIGH
Output Off Current LOW
IIH Input HIGH Current
IIL Input LOW Current
IOS Short Circuit Current (Note 1)
Power Supply Current
Total, Output HIGH
LS540
0.2
– 40
0.4 V VCC = MIN
20 µA VCC = MAX, VOUT = 2.7 V
– 20 µA VCC = MAX, VOUT = 0.4 V
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
– 0.2 mA VCC = MAX, VIN = 0.4 V
– 225 mA VCC = MAX
25 mA
LS541
32 mA
ICC
Total, Output LOW
LS540
LS541
45 mA VCC = MAX
52 mA
Total Output 3-State
LS540
LS541
52
55
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA
mA
FAST AND LS TTL DATA
5-569
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SN54/74LS540 • SN54/74LS541
AC CHARACTERISTICS (TA = 25°C)
Symbol
tPLH
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Propagation Delay,
Data to Output
Output Enable Time
to HIGH Level
Output Enable Time
to LOW Level
Output Disable Time
to HIGH Level
Output Disable Time
to LOW Level
Limits
Min Typ Max
LS540
9.0 15
LS541
12 15
LS540
12 15
LS541
12 18
LS540
15 25
LS541
15 32
LS540
20 38
LS541
20 38
LS540
10 18
LS541
10 18
LS540
15 25
LS541
15 29
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 45 pF
RL = 667 Ω
CL = 5.0 pF
AC WAVEFORMS
VIN
1.3 V
tPLH
VOUT
1.3 V
Figure 1
1.3 V
tPHL
1.3 V
VIN
1.3 V
tPLH
VOUT
1.3 V
1.3 V
tPHL
1.3 V
Figure 2
TO OUTPUT
UNDER TEST
VCC
RL
SW1
5 kΩ
CL*
SW2
VE
VE
VOUT
1.5 V
1.5 V
tPZL
1.5 V
tPLZ
≈ 1.5 V
0.5 V
VOL
Figure 3
VE
VE
VOUT
1.5 V
tPZH
1.5 V
Figure 4
1.5 V
tPHZ
≥VOH
≈ 1.5 V
0.5 V
SWITCH POSITIONS
SYMBOL
tPZH
tPZL
tPLZ
tPHZ
SW1
Open
Closed
Closed
Closed
SW2
Closed
Open
Closed
Closed
Figure 5
FAST AND LS TTL DATA
5-570
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