UP/DOWN COUNTER. SN54LS569A Datasheet

SN54LS569A COUNTER. Datasheet pdf. Equivalent

SN54LS569A Datasheet
Recommendation SN54LS569A Datasheet
Part SN54LS569A
Description FOUR-BIT UP/DOWN COUNTER
Feature SN54LS569A; SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as p.
Manufacture Motorola Inc
Datasheet
Download SN54LS569A Datasheet




Motorola  Inc SN54LS569A
FOUR-BIT UP/DOWN COUNTER
WITH THREE-STATE OUTPUTS
The SN54 / 74LS569A is designed as programmable up/down BCD and
Binary counters respectively. These devices have 3-state outputs for use in
bus organized systems. With the exception of output enable (OE) and
asynchronous clear (ACLR), all functions occur on the positive edge of the
clock pulse (CP).
When the LOAD input is LOW, the outputs will be programmed by the
parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the
counters occurs only when CEP and CET are LOW and LOAD is HIGH.
Direction of the count is controlled by the up-down input (U/D), HIGH counts
up and LOW counts down. High-speed counting and cascading is implement-
ed by internal look-ahead carry logic and an active LOW ripple carry output
(RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and
during down-count it is also LOW at binary 0. During normal cascading
operation RCO connected to the succeeding block at CET is the only
requisite. When counting and when RCO is LOW, the clocked carry output
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW
time of the clock pulse. Two active LOW reset lines are provided, a master
reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in
a HIGH state, the output control (OE) input forces the counter output into a
HIGH impedance state and when LOW, the counter outputs are enabled.
ESD > 3500 Volts
CONNECTION DIAGRAM (TOP VIEW)
VCC RCO CCO OE
20
19
18
17
YA
16
YB
15
YC
14
YD CET LOAD
13
12
11
VCC = PIN 20
GND = PIN 10
1 2 3 4 5 6 7 8 9 10
U/D CP
A
BC
D CEP ACLR SCLR GND
Note: Pin 1 is marked
for orientation.
SN54/74LS569A
FOUR-BIT UP/ DOWN COUNTER
WITH THREE-STATE OUTPUTS
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High Except RCO, CCO
IOH Output Current — High RCO, CCO
IOL Output Current — Low Except RCO, CCO
IOL Output Current — Low, RCO, CCO
54
74
54
74
54
74
54, 74
54
74
54
74
Min
4.5
4.75
– 55
0
Typ Max Unit
5.0 5.5
5.0 5.25
V
25 125 °C
25 70
– 1.0
– 2.6
mA
– 0.44
mA
12 mA
24
4.0 mA
8.0
FAST AND LS TTL DATA
5-573



Motorola  Inc SN54LS569A
SN54 / 74LS569A
FUNCTION TABLE
INPUTS
OUTPUTS
CP D C B A LOAD CET CEP U/D ACLR SCLR OE RCO CCO YD YC YB YA
XXXX
XXXX
XXXX
XXXX
H
H
H
H
L LH
LLL
HXX
LHX
H
H
H
H
H L A/R A/R
(QT – CP) + 1
Count Up
H L A/R A/R
(QT – CP) – 1
Count Down
H L H H NC NC NC NC Count Inhibit
H L A/R H NC NC NC NC Count Inhibit
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
X
X
X
X
X
X
L LH
L HH
HXH
LLL
LHL
HX L
H
H
H
H
H
H
H LL
H H H H Overflow
H L L H H H H H Overflow
H L H H H H H H Overflow Inhibit
H LL
L L L L Underflow
H L L H L L L L Underflow
H L H H L L L L Underflow Inhibit
LHLH
XXXX
XXXX
XXXX
XXXX
X XXXX
XXXX
X XXXX
X XXXX
X XXXX
L
X
X
X
X
X
X
X
X
X
XXX
HXH
LLL
LHL
HX L
XXH
LLL
LHL
HX L
XXX
H
H
H
H
H
L
L
L
L
X
H L H H L H L H Load Example
L L H H L L L L Clear (Synchronous)
L LL
L L L L Clear (Synchronous)
L L L H L L L L Clear (Synchronous)
L L H H L L L L Clear (Synchronous)
X L H H L L L L Asynchronous Clear
X LL
L L L L Asynchronous Clear
X L L H L L L L Asynchronous Clear
X L H H L L L L Asynchronous Clear
X HX X
Hi-Z Output Disabled
(QT — CP) = Output state prior to clock edge
NC = No change
A/R = Assumes required output state;
X = Don’t care
High except during Overflow and Underflow
*
DQ
R
CP Q
OE
ACLR
A
LOGIC DIAGRAM
*
YA
B * YB
C
SCLR
LOAD
D
CEP
CET
CP
U/D
*
*
FAST AND LS TTL DATA
5-574
YC
YD
RCO
CCO



Motorola  Inc SN54LS569A
SN54 / 74LS569A
DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
The four programmable data inputs.
CEP
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
CET
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
CP Clock Pulse. All synchronous functions
occur on the LOW-to-HIGH transition of the
clock.
LOAD
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
U/D Up/Down Count Control. HIGH counts up
and LOW counts down.
ACLR
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
SCLR
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
OE A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
YA, YB, YC, YD The four counter outputs.
RCO
Ripple Carry Output. Output will be LOW on
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
CCO
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
DRIVING OUTPUT
VCC
IOH
DRIVING OUTPUT
DRIVEN INPUT
IOH IIL
IOL IOL IIH
Note: Actual current flow direction shown
FAST AND LS TTL DATA
5-575







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