EDGE-TRIGGERED FLIP-FLOP. SN54LS74A Datasheet

SN54LS74A FLIP-FLOP. Datasheet pdf. Equivalent

SN54LS74A Datasheet
Recommendation SN54LS74A Datasheet
Part SN54LS74A
Description DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
Feature SN54LS74A; SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered fl.
Manufacture Motorola Inc
Datasheet
Download SN54LS74A Datasheet




Motorola  Inc SN54LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
LOGIC DIAGRAM (Each Flip-Flop)
SET (SD)4 (10)
CLEAR (CD)
1 (13)
CLOCK
3 (11)
D
2 (12)
Q
5 (9)
Q
6 (8)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
SD SD
D
OUTPUTS
QQ
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
LHXHL
HLXLH
L L XHH
HH h H L
HH l LH
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) = prior to the HIGH to LOW clock transition.
SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4 10
2 D SD Q 5 12 D SD Q 9
3 CP
11 CP
CD Q 6
CD Q 8
1
VCC = PIN 14
GND = PIN 7
13
FAST AND LS TTL DATA
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Motorola  Inc SN54LS74A
SN54 / 74LS74A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54 0.7
74 0.8
– 0.65 – 1.5
54 2.5 3.5
74 2.7 3.5
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
Input High Current
Data, Clock
IIH Set, Clear
Data, Clock
Set, Clear
20
40
0.1
0.2
Input LOW Current
IIL Data, Clock
Set, Clear
– 0.4
– 0.8
IOS Output Short Circuit Current (Note 1)
– 20
ICC Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
–100
8.0
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Clock, Clear, Set to Output
Min Typ Max
25 33
13 25
25 40
V
V
V
V
V
V
µA
mA
mA
mA
mA
Unit
MHz
ns
ns
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Test Conditions
Figure 1
Figure 1
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW (H)
tW (L)
ts
th
Clock
Clear, Set
Parameter
Data Setup Time — HIGH
Data Setup Time — LOW
Hold Time
Limits
Min Typ Max
25
25
20
20
5.0
Unit
ns
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
VCC = 5.0 V
Figure 1
FAST AND LS TTL DATA
5-73



Motorola  Inc SN54LS74A
SN54 / 74LS74A
AC WAVEFORMS
D * 1.3 V
1.3 V
th(L)
ts(L) tW(H)
ts(H)
tW(L)
th(H)
1.3 V
CP
1.3 V
1
tPHL fMAX
tPLH
Q
1.3 V
1.3 V
tPLH tPHL
1.3 V
Q
1.3 V
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
SET
CLEAR
Q
Q
tW
1.3 V
1.3 V
tPLH
1.3 V
tPHL
1.3 V
tW
1.3 V 1.3 V
tPHL
1.3 V
tPLH
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
FAST AND LS TTL DATA
5-74







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