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SN54LS74A Datasheet, Equivalent, EDGE-TRIGGERED FLIP-FLOP.DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP |
Part | SN54LS74A |
---|---|
Description | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP |
Feature | SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-T RIGGERED FLIP-FLOP
The SN54 / 74LS74A d ual edge-triggered flip-flop utilizes S chottky TTL circuitry to produce high s peed D-type flip-flops. Each flip-flop has individual clear and set inputs, an d also complementary Q and Q outputs. I nformation at input D is transferred to the Q output on the positive-going edg e of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to th e transition time of the positive-going pulse. When the clock input is at eith er the HIGH or the LOW level, the D inp ut signal has . |
Manufacture | Motorola Inc |
Datasheet |
Part | SN54LS74A |
---|---|
Description | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP |
Feature | SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-T RIGGERED FLIP-FLOP
The SN54 / 74LS74A d ual edge-triggered flip-flop utilizes S chottky TTL circuitry to produce high s peed D-type flip-flops. Each flip-flop has individual clear and set inputs, an d also complementary Q and Q outputs. I nformation at input D is transferred to the Q output on the positive-going edg e of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to th e transition time of the positive-going pulse. When the clock input is at eith er the HIGH or the LOW level, the D inp ut signal has . |
Manufacture | Motorola Inc |
Datasheet |
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